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rom_fft
采用xilinx的ROMIP核产生类似正弦信号,经过FFt后可以观察结果(Using the xilinx ROMIP nuclear generating similar sinusoidal signal can be observed through the results after FFt)
- 2013-09-14 20:59:03下载
- 积分:1
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用vhdl来实现的数字频率合成的技术,几乎很全的,所有的都有...
用vhdl来实现的数字频率合成的技术,几乎很全的,所有的都有 -Use VHDL to realize the digital frequency synthesis technology, almost the whole of, all have
- 2022-02-04 17:07:58下载
- 积分:1
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Uses Verilog the HDL design, obtains the realization basis on
the palm space int...
采用Verilog HDL设计,在掌宇智能开发板上得到实现
根据抢答器的原理,整个电路可划分为三部分:采样电路、门控电路和译码电路- Uses Verilog the HDL design, obtains the realization basis on
the palm space intelligence development board to snatch the answering
principle, the entire electric circuit may divide is three parts: The
sampling electric circuit, the gate control the electric circuit and
the decoding circuit
- 2022-03-16 23:36:15下载
- 积分:1
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chuankou
说明: 本实验为UART回环实例,实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx,以及时钟产生模块clk_div。uart_rx将收到的包解析出8位的数据,再传送给 uart_tx发出,形成回环。参考时钟频率为100MHz,波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分:1
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codings
wavelet transform of a signal,it is important and useful code to trans form frequency to time domain
- 2013-11-10 15:10:32下载
- 积分:1
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vhdl
vhdl code for internet interface
- 2014-12-04 04:58:04下载
- 积分:1
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fft_32k_readme_v1_0_0
Fast Fourier Transform (FFT) 32K Point Design contains
information about the design example
- 2018-10-11 15:11:54下载
- 积分:1
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乐曲演奏电路,可以播放歌曲在数码管上显示相同的时间…
乐曲演奏电路,能演奏歌曲,同时在数码管上显示演奏的乐曲音符的数字。-Music concert circuit, can play songs at the same time in the digital tube displays the number of notes played music.
- 2023-01-23 08:45:03下载
- 积分:1
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tdc
线性伸展TDC的verilog,包含门级网表(TDC linear stretch of verilog, includes gate-level netlist)
- 2021-01-04 18:58:55下载
- 积分:1
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mux21a
在VHDL结构体中用于描述逻辑功能和电路结构的语句分为顺序语句和并行语句两部分,顺序语句的执行方式十分类似于普通软件语言的程序执行方式,都是按照语句的前后排列方式顺序执行的。(VHDL structure in the body used to describe the logic function and circuit structure of the order of statements and expressions are divided into two parts in parallel statement, modalities for the implementation of the order of statement is very similar to ordinary language software program implementation, are in accordance with the statements before and after the arrangement of the order implementation.)
- 2008-12-24 18:25:20下载
- 积分:1