一个FPGA

实现arm与fpga之间通过gpmc总线通信(the device of fpga)

8路视频光端机 接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。-8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission.

Diagram and how-to-make instructions pack of 6 diferent Amplifiers

VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.

利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。(Design using Verilog HDL language a taxi meter, it has time display, billing and simulation taxi start, stop, reset and other functions, and set dynamically display scanning circuit and the corresponding time fare, shows the hardware description language Verilog-HDL design advantages of digital logic circuits.)

基于FPGA的JPEG解码，对开发图片解码的人有用。(FPGA-based JPEG decoding, the development of image decoding useful.)

一个可以使用的RocketI/O开发实例。基于Xilinx FPGA Virtex5平台。-One can use RocketI/O development example. Based on Xilinx FPGA Virtex5 platform.

卷积码（2,1,4）编解码的FPGA实现(Convolution code (2,1,4) decoding the FPGA implementation)

32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools

FPGA实现串口发送 Verilog 语言(Serial reception FPGA Verilog language.)