基于FPGA的快速傅立叶变换实现，适合fpga工程技术人员参考设计...

通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)

华为内部资料，关于FPGA设计的详细过程介绍，很不错的。本文档从FPGA器件结构出发以速度路径延时大小和面积资源占用率为主题描述在FPGA设计过程中应当注意的问题和可以采用的设计技巧。(Huawei internal information, with regard to detailed FPGA design process of introduction, it is good. This document from the FPGA device structure in order to speed the path delay and area the size of the theme of the occupancy rate of resource description in the FPGA design process should pay attention to the problems and design techniques can be used.)

9对于输入密码锁的键，假设复位后七个灯显示" 0"，使用sw1、sw2、sw3、sw4 4，只需按下并松开任意sw1、sw2键，使七个灯显示值加" 1"，只要按下并松开任意sw3、sw4，将使七个灯显示值加" 2"

VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners

基于NIOS II 的DE1开发板的VGA 控制器VGA控制模块主要控制VGA模块的开始和其运行的状态，需要写一个Avalon 从端口响应CPU的控制信号，继而控制整个模块的运行，-Based on the DE1 of the NIOS II development board VGA controller to control the VGA module VGA main control module and its operation began, and the need to write a response to Avalon from the CPU ports of the control signal, and then control the operation of the entire module,

典型事例，从网上down的，希望对大家有用，-Typical examples, from the Internet down, and I hope useful for everyone,

VIP FPGA板的配套例子，这个是VGA格式lcd液晶屏幕显示用。(VIP board supporting example of this is the VGA format PREVIEW.)

使用vriloge硬件描述语言设计数字频率计，其对于高频测量精确，可测范围0―99999999HZ，在MAX+PLUSII中运行通过并在实验箱上运行通过达到要求-The use of hardware description language design vriloge digital frequency meter, and its high-frequency measurement for accurate, range 0-99999999HZ, in MAX+ PLUSII run me through and run the experiment to meet the requirement through

Simple ALU Objectives 1. Explore simple ALU structure. 2. Working with components 3. Working with language templates in ModelSim 4. Making a test bench and simulation using ModelSim

由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)