基于FPGA的快速傅立叶变换实现，适合fpga工程技术人员参考设计...

EMIF接口调试代码，使用的是Verilog语言，FPGA与DSP通信，测试成功(EMIF interface debugging code that USES the Verilog language, FPGA and DSP communication, testing success)

this a LCD Driver VHDL code -this is a LCD Driver VHDL code

龙芯CPU+IP+资源简介，希望大家能够了解自己开发的芯片。(Godson CPU+ IP+ Resource profile, hope that we can understand their own chips.)

比较适合初学学者，而且比较基础。描述的不全面，先看看吧-it‘s best book for beginner！

modelsim设计的可调占空比的方波程式-modelsim designed adjustable duty cycle of the square wave program

altera DE1 SD_CARD带写入一个扇区功能的程序，已确认成功，下载直接运行就可以看效果-altera DE1 SD_CARD with a sector write function procedures, has confirmed the success of running can be downloaded directly watch the effect of

VHDL语言编写的FIR滤波器源码 对于嵌入式设计者有很好的指导作用 -VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding

入门，verilog语言，实现字符型液晶1602的显示，及按键控制-verilog

在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.

说明：  串口通信通用模块，FPGA Verilog语言 ise，vivado环境(uart,FPGA Verilog, ise,vivado)