一种链式Merkle签名加密处理器体系结构

TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus

4位MCU AM2901的完整VHDL程序，AM2901为主程序，其他为实体库-4 MCU AM2901 complete VHDL program, AM2901-based procedures, other entities, the Treasury

说明：  用于读取海德汉绝对位置编码器的位置数据。ENDAT2.1接口(Read the data from ENDAT2.1)

说明：  用MATLAB设计及FPGA实现IIR滤波器的方法 摘要 本文介绍了IIR数字滤波器的传统设计思想与步骤及计算机辅助设计方法。并在FPGA上高效实现的低阶IIR滤波 器，其阶数低，实时响应快，适合雷达等的实时、高效处理环境。利用IIR滤波器的多相结构来实现该滤波器系统的方法，对于 四通道的情形在MATLAB上利用Simulink作了仿真, 并在目标板上对算法进行了实现,证明该系统能够同时处理四个通道的信号。(Using MATLAB Design and FPGA realization IIR Filter method Abstract This paper introduces IIR digital filter traditional design Thought and steps and CAD method. And FPGA on efficient realization low IIR filter, its order low, real response fast suitable radar real time, efficient processing environment. Use IIR filter multiphase structure realize the filter systematic method, for four channel circumstances in MATLAB on use Simulink made simulation and target board algorithm was realized proved system can simultaneously four channel signal.)

ASK,FSK,PSK,DPSK调制解调的详细仿真代码(ASK, FSK, PSK, DPSK modulation and demodulation detailed simulation code)

This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.

vga很好的学习材料，测试程序，欢迎下载(vga good learning materials, testing procedures, please download)

FPGA驱动adc9226，高精度高速度。(ad9226 by FPGA)

RAM读写控制器，用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram

基于VHDL编写的10进制显示输出，基于16进制的10进制控制，适合初学者(VHDL-based display output written in decimal, hexadecimal, 10 hexadecimal-based control, suitable for beginners)