波特率选择VHDL源代码没有错误调试

说明：  用FPGA进行等精度频率和相位差测量的程序，本程序是在EPEC6Q240C8下的程序(Carried out with the FPGA such as the frequency and phase measurement precision of the procedure, this procedure was the procedure under the EPEC6Q240C8)

基于fpga的出租车计费系统，采用自顶向下的设计方法-FPGA-based billing system of a taxi, using top-down design methodology

URISC 处理器由数据单元和控制单元组成。数据单元中包含保存运算数据和运算结果的数据寄存器，也包括用来完成数据运算的组合逻辑电路单元。控制单元用来产生控制信号序列，以决定何时进行何种数据运算。控制单元要从数据单元得到条件信号，以决定继续进行那些数据运算，数据单元要产生输出信号，数据运算状态等有用信息。-URISC processor by the data unit and control unit. Data unit included in the preservation of data and computing the results of computing the data register, but also data used to complete a combination of computing logic circuit unit. Control unit used to generate the control signal sequence, to determine when and what data computing. Control unit from the data unit received condition signal to determine the continuation of the data computation, data unit to produce output signals, data, such as computing the state of useful information.

vhdl 中各种数据类型的转换实现,可以调用函数库实现-date type change

这是一款CPLD的在线调试软件。能够满足用于学习者的一般要求。-This is a debugging software online CPLD. Be able to meet the general requirements for learners.

在altera DE2 的开发板上采集图像，到lcd显示的原程序 。-In altera DE2 development board collecting images, lcd display to the original procedure.

高效的同步有限状态机的设计，本代码详细的说明了如何设计高效和规范的fsm设计-Efficient Synthesizable Finite State Machine Design using NC-Verilog

Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download

使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.

ByteBlasterII 下载线的制作-Download ByteBlasterII production line