用vhdl编写的简易电子中设计，经过测试成功，且用记事本上载，无需阅读器进行阅读。

APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)

一个PS2 IP CORE(VHDL) for FPGA-A PS2 IP CORE (VHDL) for FPGA

mike11河道断面处理软件，将断面格式写成11要求的格式(MIKE11 river section processing software, the section format 11 format )

音频spdif格式编解码，可以将音频格式在i2s dsd以及spdif之间转换(Spdif audio codec)

Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis

基于FPGA 16QAM解调verilog代码，(16QAMdemoluator veriliog)

EDA/VHDL数字频率计，可编程逻辑门阵列，EDA课程设计(EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design)

讲解快速傅里叶变换--FFT快速算法的文章。-On Fast Fourier Transform- FFT fast algorithm for the article.

spartan-3e vhdl fpga 输入用滑动按钮代替 输出用led代替(spartan-3e VHDL fpga input with sliding button instead of the output with led instead)

全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.