用vhdl编写的简易电子中设计，经过测试成功，且用记事本上载，无需阅读器进行阅读。

利用Verilog编写一个交通灯控制电路，能控制两条路上红、黄、绿灯的变化，并且显示等待时间(Using Verilog HDL to design a traffic light control circuit. It can control the change of red, yellow and green lights on two roads, and display the remaining waiting time.)

基于vhdl编写的贪吃蛇游戏，课程设计必备(Based on the VHDL language of the snake game, curriculum design essential)

verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)

verilog产生高斯白噪声，gwn_en信号产生使能，gdata是幅度服从高斯分布，功率谱密度为定值的高斯白噪声序列，共10位（现实中只能够做到带限，跟dac输出带宽有关，我的系统只能做到300kHz）(verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence value, a total of 10 (in reality can only be band-limited, with dac output bandwidth related, My system can do 300kHz))

说明：  matlab code for JTAG cable checking

基于DE2_70平台，编写nios软核c代码，控制流水灯，硬件实现验证通过，适合入门(Based DE2_70 platform, written nios soft core c code, control water lights, verified by hardware implementation, suitable for entry)

FPGA（现场可编程门阵列）在医疗系统中得到广泛的接受

SPI Verilog code with programmable clock

cordic算法的vhdl实现，内附有文档说明-cordic algorithm vhdl realized, a document containing a note

是用于pci开发的核，可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间 (Pci developed for nuclear, hardware information can be mapped to the inter-ran up to save the developers time to understand the hardware)