vhdl描述的显示代码 maxplus2开发环境

用VHDL实现了希尔伯特滤波器,即就是幅度不变，而相位移动90度(use vhdl to accomplish the hilbert filter)

n_bit_paralleLoadShiftRegJK

说明：  实现AXI,AXI-Lite乒乓地址的传输，AXI,AXI-Lite已经封装成内核，可直接修改后使用(Realize the transmission of table tennis address of Axi and Axi Lite. Axi and Axi Lite have been encapsulated into a kernel, which can be directly modified and used)

基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来(Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it)

基于对ROM的编写，在quartusII上实现九九乘法器的实现，在试验箱的四个数码管上分别显示乘数，被乘数，积

SPI接口VHDL代码,内有说明,很详细.-SPI interface VHDL code, which has made it clear that, in great detail.

basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)

通过编写verilog语言完成数据的在液晶LCD1602显示(By writing verilog language to complete the data displayed on the LCD LCD1602)

Efficient_Digital_Implementation_of_Extreme_Learning_Machines_for_Classification

以太网控制器verilog，含有mac,mii接口(Ethernet controller verilog, containing mac, mii interface)