VerilogHDL,对初学者很有帮助的,可以一下的!

Quartus环境下多路选择器的编写代码，适合初学数字逻辑设计的进行学习(MUX in Quartus)

codic algorithm,which is used to calculate triangular functions

URAT VHDL程序与仿真 URAT the VHDL program and Simulation (URAT the VHDL program and Simulation )

FSK模拟信号源，利用ISE7.1或以上环境打开。(FSK signal simulator.The project can be open in ISE7.1 or upgrade version.)

SPI接口的实现以及对外设的读写操作，其中包扩了几种工作方式，同时可以读取外设的版本号，传输速率可以达到2Mbps-SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer rate up to 2Mbps

verilog 写的 “梁祝”乐曲演奏电路-verilog wrote " The Butterfly Lovers" music concert circuit

电梯的vhdl设计，6层楼含开关门，警报，内部请求，外部请求-Vhdl elevator design, six floors with switch doors, alarm, internal requests and external requests

可以实现2PSK的信号调制，已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)

多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)

Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways. -Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.