VHDL语言描述的二进制十进制译码电路，已经编译完成

说明：  实现ARP、ICMP、UDP、TCP、IP和MAC全过程的传输，对TCP的连接、接收、发送、断开均经过测试，功能正常(Realize the transmission of ARP, ICMP, UDP, TCP, IP and MAC in the whole process, test the connection, reception, transmission and disconnection of TCP, and the function is normal)

说明：  amba总线桥:ahb to asb!verilog hdl文档加代码，非常全，soc(amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc)

说明：  Verilog实现的加减法功能计数器，通过独立的自增自减信号控制计数器进行自增计数和自减计数(Function counter of addition and subtraction implemented by Verilog)

Interface for ADS8361 TI ADC IP Core for ALTERA NIOS2

这是一个AMBA APB桥实现VHDL。这包括主人，奴隶和试验台试验桥。我已经测试功能。

本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.

该程序用vhdl编写的vga显示的小游戏，到时屏幕上会显示一个小球，一根棒子，一面墙，棒子可以通过按键控制来移动。而小球在不停的运动，遇到墙会反弹。(Game written by the program with VHDL VGA display, the screen will display a small ball, a stick, a wall, stick to move through the key control. Ball in constant motion, encountered the wall will bounce.)

说明：  verilog语言编写的dac5687的接口程序，串行模式控制。(written dac5687 verilog interface program, serial mode control.)

verilog实现rtc文档，可用于实现RTC。(verilog realize rtc document can be used to implement the RTC.)

HDB3 ENCODING AND DECODING METHOD