Digital Design and Modeling with VHDL and Synthesis

资源描述这个秒表特点是计数到59分59秒9，并且有可以让计数暂停和清零。采用了二分频，六进制和十进制组合，加上扫描电路设计而成的。

实现千兆以太网数据发送，通过GMII接口向PHY写数据，控制PHY发送数据。(Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.)

说明：  BUS documentation and map reffereces

说明：  FPGA和双端口RAM的DDS任意波形发生器的实现(FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator)

说明：  FIFO: First in, First out 代表先进的数据先出，后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO，根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)

基于Verilog的图像采集、处理和存储程序，初学者参考，高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)

说明：  常系数有限域乘法器，verilog DHL源码(Constant coefficient finite field multiplier, verilog DHL source)

this program is a simulation for Aloha

11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated

buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键-buffer_display is 4X4KEYPAD output module. It showed six consecutive Press