使用CORDIC实现三角函数计算，使用VHDL语言实现

FPGA to design in ECU, very help for engineer

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE

成功解决FPGA设计时序问题的三大点.word说明文档，很详细(FPGA design timing problems successfully solved the three points)

flv的vhdl教学文件:在线调试 自己慢慢欣赏吧-flv file of VHDL Teaching: Online debug their慢慢欣赏吧

You well get all details about project and microcontroller

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设计一4位比较器,画出门级电路图,用verilog语言完成设计。 (Design a four comparators, drawing out level circuit diagram, complete the design using verilog language. )

一个简单的键盘接口模块程序，对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)

关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL

初学学习verilog的经验，可以帮助新手以正确的思维方式，学习方法学习。(Verilog learning experience)