the booth algorithm to implement the 32bit 's multiplication.

QPSK调制的载波频偏估计，是一个可以调用的函数。接收端进行了一系列的处理。经典的Kay法(QPSK-carrier frequence offset estimation_ kay )

可以直接下载到芯片用的带有FIFO的完全UART程序，vhdl语言编写。-Can be directly downloaded to the chip used in the complete UART with FIFO procedures, vhdl language.

说明：  实现简单的硬件加法器、除法器，实现源码文中注释(Realize simple hardware adder and divider, realize source code)

实现有限域中乘法，输入二个普通二级制数，输出在本原多项式的乘法结果(Achieve limited multiplication field, enter the number of two-tier system of two ordinary output in primitive polynomial multiplication results)

通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)

使用VHDL语言，对Altera公司的DE2开发板进行开发，本例实现了对板上7段数码管的显示，在niosiiIDE上基于硬件实现小灯的循环亮灭-Using VHDL language, on Altera s DE2 development board for development, which in this case the realization of paragraph 7 of the on-board digital tube display, in niosiiIDE hardware implementation based on a small circle of bright lights out

FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)

内置自修复分析仪

酷睿系列流水灯通用程序，来回往返流水，点亮led(ledwater for ep2c8q208c8)

基于 verilog的卷积运算代码，应用于离散小波分析。(verilog conv)