the booth algorithm to implement the 32bit 's multiplication.

Verilog 最大公约数设计RTL级代码和芯片设计图(Verilog GCD Design and synthesis layout )

说明：  高速流水的SDRAM控制器，最高速度可达速度在200M左右(high speed SDRAM controller)

基于Verilog的FPGA时钟分频程序(FPGA clock frequency division program based on Verilog)

数字时中（VHDL）-Numbers in (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

PC104总线的CPLD代码，调试已经通过，可以修改应用到其他的工程(PC104 bus CPLD code, debugging has been passed, you can modify the application to other engineering 示例用法:)

IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

一个LED大屏幕接收卡的完整设计工程,有需要学习LED大屏幕控制的朋友可以参考

4X4keypad的防抖动模块，用于假按键的检测-4X4keypad shake the module, the keys for false detection

利用高速口GTX进行快速的数据传输，包括接受和发送模块，用途广泛(The use of high-speed port GTX for fast data transmission, including receiving and sending modules, has a wide range of uses.)