the booth algorithm to implement the 32bit 's multiplication.

dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, clock demo. code test.

cic设计 verilog verilog(cic verilog design verilog)

浮点数 矩阵乘法模块 verilog语言编写 可直接调用(Floating-point matrix multiplication module can directly call verilog language)

此代码能够使得键盘控制液晶，实时的进行书写，按下Backspace清屏(This code enables the keyboard to control the LCD, in real-time writing, press Backspace clear the screen)

Quartus环境下使用Verilog编写的HDB3编解码程序，RTL和时序仿真已过(Quartus under the environment of a HDB3 protocol procedures written in Verilog, RTL and timing simulation has be passed)

6713emiftofpgatopci,这个是完整的一套从6713的emif到fpga的双口ram，然后主机通过9054到双口ram，交换数据完成-6713emiftofpgatopci, this is a complete set of the EMIF from 6713 to the FPGA

v6 1x 3.125G rapidio协议工程代码(xilinx v6 rapidio data transmission protocol Practical project application engineering code)

protel中fpga封装库3，非常难找的-protel library in fpga package three, very difficult to find the

vhdl学习方法,含有大量的vhdl源代码,对vhdl的语法的介绍-VHDL source习laugh Yang, Yi bleed at the nose cavity submerged stresses measured tungsten Daitou VHDL, VHDL-Qin Pang Yang cavity cavity Geng Zhuang

Efficient_Digital_Implementation_of_Extreme_Learning_Machines_for_Classification