可以用于按键去抖动的电路应用，采用vhdl编写

6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard

黑金FPGA助学版-tcl,包含开发板所有管脚。不需要再对板子管脚定义。AX301(Black Gold FPGA Student Edition-tcl, development board contains all the pins. No need for a board pin definitions. AX301)

spartan605评估板测试代码。xilinx官方资料(spartan605 uation board test code)

数字电子钟用自拍图像代替了内置图像的石英制作

实施256点，

matlab dsp building 工程欢迎下载(matlab dsp building )

使用430的四系点亮流水灯，内置有时钟函数，函数简单，值得一看(The four lines using 430 lit water lights, built-in clock function, the function is simple, eye-catcher)

用verilog 语言编译16QAM调制(a great complied code of 16QAM modulation for OFDM)

FPGA对SDRAM进行读写测试程序，亲测有效无误。(FPGA reads and writes test programs for SDRAM.)

vhdl例程代码大全，包含流水灯，数码管，AD,DA转换等(Guinness vhdl code routines, including water lights, digital, AD, DA conversion)