介绍了FPGA设计的十大准则，对初学者很有用，对于工作多年的同志，也会有整理总结的好处...

上海交大关于基于FPGA的DSCDMA的实现的毕业设计(Shanghai Jiaotong University based the FPGA DSCDMA, achieve graduation design)

Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!

华为_大规模逻辑设计指导书，看看人家是怎么管理FPGA编程的，真的获益匪浅-Huawei _ large-scale logic design guide book, take a look at how the management of people FPGA programming, and really benefited from

双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources. Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y)

这个代码主要实现了基于VHDL的关于TV方面的功能。(This code is the main achievement of the VHDL about aspects of the function based on TV.)

说明：  fpga实现相关滤波算法中的CSK算法，采用仿真的方式验证结果 fpga是xilinx 仿真工具是vivado2018.2 语言是verilog(The CSK algorithm is implemented in FPGA, and the results are verified by simulation FPGA is Xilinx The simulation tool is vivado 2018.2 Language is Verilog)

关于I2C总线协议的verilog代码，里面包括了3个verilog代码(I2C bus protocol verilog code, which includes three verilog code)

用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0

关于语音通信信道调制的程序代码，是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)

verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等(verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other)