介绍了FPGA设计的十大准则，对初学者很有用，对于工作多年的同志，也会有整理总结的好处...

自己写的扩展功能时钟，增加了年、月日计时，verilog代码，已在spatarn3实现。-Write their own extensions clock, an increase of the year, month day time, verilog code in spatarn3 realize.

三层电梯的详细电路 Foundation版 包括强行开关门打断(Elevator control Foundation project)

具有桥式结构的传感器很多，如利用应变原理、磁电阻原理和其他变电阻原理的传感器，可以实现对压力、位移、加速度、磁场等物理量的测试。这种结构的差分输出可以增加灵敏度，也有一定抵消外加干扰的能力。而且有的虽不是差分输出，比如电阻分压式的输出，可以认为是“半桥”，我们还可以人为的加上另一半，即加上一对精密电阻和一个电位器组成另一个分压电路，形成差分输出。每次调节电位器使差分输出为0，抵消零磁电压。-Bridge structure with many sensors, such as the use of contingency theory, the principle of magneto-resistance and other variable resistance sensor principle can be achieved on the pressure, displacement, acceleration, magnetic field, such as physical tests. The structure of the differential output can increase sensitivity, but also have some ability to offset the additional interference. And some is not a differential output, such as pressure resistance of the output type, you can think is

一个可综合的同步FIFO的verilog源代码-An integrated synchronous FIFO in Verilog source code

HDLC的一些相关文档，可能对HDLC设计有很大的帮助！-HDLC some relevant documents, HDLC design may be very helpful!

说明：  FPGA串口实现。 发送和接受数据功能代码(FPGA serial interface. Send and receive data function code)

TASKS OF TWO TYPES CAN BE RUN FOR EVERY 2 MIN.

FPGA用于实现crc16编码的verlog源程序，用到的请下载。(FPGA is used to achieve the the crc16 the encoding of verlog source code used to download.)

LATTICE FPGA FIFO 程序例程，工程详细，全部源代码上传 (LATTICE FPGA FIFO routine, detailed engineering, all source code uploaded)

在nios系统开发中的驱动i2c音频电路的代码,包括verilog代码,与相应的驱动代码(In the nios system development in the driver i2c code for the audio circuitry, including the verilog code, and the corresponding driver code)