Verilog 经典实例，完整源码与大家分享

说明：  基于FPGA的液晶显示控制器的设计，FPGA用的是EP2C5,LCD用的是ST7920内核的122*32点阵的LCD，显示中西文字符(FPGA-based LCD display controller design, FPGA is used EP2C5, LCD is used in the ST7920 core of 122* 32 dot matrix LCD, display of Chinese and Western characters)

多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)

FPGA编写的三角波发生器，可以产生100HZ～500KHZ以上的三角波，波形稳定(FPGA prepared triangular wave generator, can produce more than 100HZ ~ 500KHZ triangle wave, waveform stability)

《Verilog HDL 程序设计教程》6-"Verilog HDL Design Guide" 6

40M时钟输入经过iserdes倍频到960M(input 40M o clock and output 960M )

5604FPGA驱动，能显示数字（5604里面为4个595）(5604 FPGA driver, able to display digital (5604 contains 4 595))

用VHDL语言编写的实现8位数据的并串转换，可下载在FPGA中-VHDL language with the realization of an 8-bit data, and the string conversion, can be downloaded in the FPGA in

说明：  uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)

Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download

FPGA 数码管接口例化编程，学习初级入门verilog编程技术(FPGA 数码管接口例化编程)