Verilog 经典实例，完整源码与大家分享

使用VerilogHDL语言加上IP核产生PWM调制波，占空比和频率可调。(The PWM modulation wave, duty cycle and frequency can be adjusted by using VerilogHDL language and IP kernel..)

USB IPcoreIP核 包含文档(带说明)-USB IPcoreIP core includes a document (with instructions)

uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)

基于MAX2运用Quartus实现串口通信-MAX2-based use of Quartus Serial Communication

this come from alter ,you can look and find it on line about jtag.

流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）(Multiplier and adder pipeline development environment: Modelsim (verilog hdl))

说明：  ad9649的fpga驱动程序,FMC接口，基于Xilinx KC705(AD9649 Evaluation Board, FMC Interposer & Xilinx KC705 Reference Design)

通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)

FPGA读SRAM中的数再传给CY7C68013-Reading SRAM in the FPGA, then pass on a few CY7C68013

stbc空时编码源码，非常好的程序。verilog程序-STBC Space-Time Coding Source, very good program. Verilog program