Verilog 经典实例，完整源码与大家分享

FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.

vhdl 中各种数据类型的转换实现,可以调用函数库实现-date type change

基于单片机的DDS信号发生器，具有DDS思想的单片机编程。。。(Sunplus based DDS signal generator with DDS thinking microcontrollers. . .)

基于FPGA的超声波测距，通过数码管显示距离(FPGA-based ultrasonic distance)

这是这本书的第四个版本，现在这个版本不仅提供了VHDL语言的覆盖面，但设计方法的信息，以及。此版本将指导读者通过创建一个VHDL设计的过程中，模拟设计，综合设计，放置和布线设计，使用的重要模拟验证的最终结果，新的技术，称为全速调试，提供了极其快速设计验证。在这个版本的设计，例如已被更新(This is the fourth version of the book and this version now not only provides VHDL language coverage but design methodology information as well. This version will guide the reader through the process of creating a VHDL design, simulating the design, synthesizing the design, placing and routing the design, using VITAL simulation to verify the final result, and a new technique called At-Speed debugging that provides extremely fast design verification. The design example in this version has been updated to reflect.)

包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 (DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!)

说明：  本代码是控制DS1302的VHDL代码，浅显易懂，方便修改，注意看data sheet，保证时钟和各个延迟满足要求即可(This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the various delays)

该程序用来实现电话计时以算取费用，比较简单(telephone cost metering verilog code)

本文是Altera公司编写的dspbuilder的设计方法，但是是英文原版的(This article is prepared by Altera Corporation dspbuilder design method, but it is the original English edition of)

这是基于Quartus2 开发环境和verilog hdl语言写的38译码器(This is based development environment and Quartus2 verilog hdl language used to write decoder 38)