a code to display in VGA using VHDL lang

xilinx 平台的SPI从接口实现源码，供参考学习(used xilinx,slave-spi interface.)

自己编写的经过QuartusII验证的Verilog HDL程序，可以实现常见功能-After QuartusII their written procedures for verification of the Verilog HDL, can achieve common features

one of example about hardware design language

基于FPGA的图像压缩算法程序，自己写的，可以参考一下(FPGA-based image compression algorithm, write your own, you can refer to)

设计遥控器接收解码电路。该电路接收编码后的串行数据，解码输出数据。电路接收 到的串行数据的格式为： 4 位同步码“ 1010”， 4 位数据（高位在前）， 1 位奇校验码（对前 8 位数据校验）(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial data received by the circuit is: 4 bit synchronous code "1010", 4 bit data (high in the front), 1 bit parity check code (check for the first 8 bits of data))

出租车模块设计加nios2设计cup程序代码 出租车模块设计加nios2设计cup程序代码-Taxi modular design design cup plus nios2 code taxi modular design design cup plus nios2 code

LCD显示超级玛丽游戏2 (LCD display Super Mario game)

分频器的VHDL程序，完整的建立工程，编译，功能功能仿真，验证-fenpinqi de vhdlchengxu gongnengfnagzhen,yanzheng

RSA密码芯片的FPGA实现[1].part1.rar RSA密码芯片的FPGA实现[1].part1.rar-RSA password chip FPGA realization of [1]. Part1.rarRSA password chip FPGA realization of [1]. Part1.rar

用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0