自己编写的经过QuartusII验证的Verilog HDL程序，可以实现常见功能...

基于BOOTH的32位快速乘法器的设计源码-BOOTH-based 32-bit fast multiplier design source

URAT VHDL程序与仿真 URAT the VHDL program and Simulation (URAT the VHDL program and Simulation )

dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies

用Verilog语言编写的产生正弦波和方波的程序(Generate sine and square wave Verilog language program)

步进电机驱动，32等级速度，带加减速度控制。verilog编写。(step motor driver,32 level speed.)

8级cordic 算法verilog (8 cordic algorithm verilog)

vga很好的学习材料，测试程序，欢迎下载(vga good learning materials, testing procedures, please download)

应用硬件描述语言产生随机数，在模糊控制仿真中应用的较多-By VHDL generating random Numbers, in the application of the fuzzy control simulation

4 bit convoltion with vhdl.

Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!