自己编写的经过QuartusII验证的Verilog HDL程序，可以实现常见功能...

VHDL控制VGA 在显示器上显示图形，分辨率800X600，晶振50Mhz-VGA control with VHDL

红色飓风II开发板USB2FPGA USB驱动程序，由verilog编写，包括源码和FIFO测试程序(Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO)

ad9850函数发生器 MSP430单片机驱动程序 扫频 DDS(AD9850 DDS)

verilog 编写基于SRAM(CY7C1041)的代码-Verilog prepared based on the SRAM (CY7C1041) code

利用FPGA内核产生SPWM波，并且频率可调(The FPGA kernel is used to generate SPWM waves, and the frequency is adjustable)

利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)

说明：  RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)

说明：  THU微纳电子系ic设计课程大作业，使用verilog实现CNN加速器，含一层卷积和池化，仿真通过。(a CNN accelerator written in VerilogHDL, including one conv layer and one pooling layer, simulation passed)

用verilog写的卷积码的编码程序以及viterbi译码程序(Use verilog write convolution code coding procedures and viterbi decoding program)

designing of 16 bit adder using 4 bit adder using verilog code