fenpinqi de vhdlchengxu gongnengfnagzhen，政

中频70M，30M带宽LFM信号，采样率为102.4M，，数字下变频后，还进行了三倍抽取，最后还得到I，Q两路信号 (IF 70M, 30M bandwidth LFM signal, the sampling rate 102.4M, under digital variable frequency after also carried out three times extracted, and finally also received the I and Q signals)

verilog HDL 4×4矩阵键盘驱动程序包括硬件电路图-verilog

verilog da0832 cpldfpga control-verilog da0832 cpldfpga control

adc器件ads62p49配置代码，已在工程中验证可用(Temperature sensor DS18B20 parses the code, has verified the ADC device configuration code, has been verified available)

此压缩包里面有基于vivado平台的工程，包括了正弦信号的产生，还有fir滤波器的设计以及fft算法的设计实现(in this package,there are three projects of the generation of the signal of sin and the design of fir filter and the ari)

自写的巴克频带滤波器组代码，生成频带滤波器组。内涵debug：输出生成的滤波器(Barker band filter bank code that generates band filter bank. Connotation debug: output generated filter)

实现千兆以太网数据发送，通过GMII接口向PHY写数据，控制PHY发送数据。(Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.)

HDLC通信协议，FPGA实现，包含源文件和仿真测试文件。(HDLC comunication)

说明：  用FPGA进行等精度频率和相位差测量的程序，本程序是在EPEC6Q240C8下的程序(Carried out with the FPGA such as the frequency and phase measurement precision of the procedure, this procedure was the procedure under the EPEC6Q240C8)

Verilog reference book