DC motor controller is excellent VHDL source code can be sown in simulation tool...

我上期做的VHDL设计方案，用于在FPGA或CPLD中实现HDB3的编码-I do view on the VHDL design options for the CPLD or FPGA to achieve HDB3 code

FPGA锁相环实验： 顶层文件加底层IP文件构成 top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)

说明：  基于蜂鸟E203riscv系统的DMA外设代码(DMA code based on hbird_e203 system)

xilinx SP6系列的3-8译码器实现(Implementation of Xilinx SP6 Series 3-8 Decoder)

针对串行存储器M25P80应用的verilog程序-M25P80 serial memory for applications Verilog program

三层电梯的详细电路 Foundation版 包括强行开关门打断(Elevator control Foundation project)

用于数字积分器的设计，主要涉及VHDL、Verilog等FPGA编程语言。(Design of Digital Integrator)

在Qaurtus环境下用Verilog输入实现64QAM信号的发生，用MATLAB协助验证，观察了PN序列对应的星座图。(Simulating generation of 64QAM RF Signal in Quartus II IDE,identified with MATLAB,constellation gram displayed.)

quartusii 三分频电路，大家帮参考一下，有什么问题-one-third of quartusii frequency circuit, refer to U.S. help, have any problem

VCS详细学习资料。内涵专业研究院所内部培训资料。适合于初学者学习使用，易于上手。(VCS learning)