DC motor controller is excellent VHDL source code can be sown in simulation tool...

16位的移位寄存器，加上testbench,可以在modelsim里面运行~-16 of the shift register and testbench, modelsim the inside running ~

v6 1x 3.125G rapidio协议工程代码(xilinx v6 rapidio data transmission protocol Practical project application engineering code)

Xilinx Sysgen User Guide

TASKS OF TWO TYPES CAN BE RUN FOR EVERY 2 MIN.

FPGA读取LM75A温度数据，并在段码LED上实时显示。(The temperature data of LM75A are read by FPGA and displayed on segment code LED in real time)

CODE_VHDL_INITIALIZING 液晶电视 DISPLAY(KHỞI TẠO HIỂN THỊ LCD)

硬件设计VHDL学习100例(站长推荐)-VHDL hardware design study of 100 cases (chief recommended)

ALTERA上DE2平台，利用内部50M Hz时钟，在数码管模拟显示时间(时分秒)。-ALTERA on DE2 platform, using internal 50M Hz clock, in the digital control simulation show time (hours minutes and seconds).

此程序为串行通信程序,采用verilog语言编写的,经过仿真验证已经通过.-This procedure for the serial communication procedures, the use of Verilog language, after simulation has been adopted.

这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.(This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.)