看了好多网了，发现有2to4译码，3to8译码，今天我要用4to16译码，写完了就发了上来...

该部分的主要功能是完成基于FPGA的polar码SC译码。(The main function of this part is to complete the FPGA-based polar code SC decoding.)

UG二次开发，课程作业，研究生，学习，初学者，打孔，复杂体，阵列 UG C program，homework，student，study，first，hole，complex，many( UG C program，homework，student，study，first，hole，complex，many)

实现拟想要的音乐，基于at89s51单片机的电子琴设计！(To achieve the desired music to be based at89s51 keyboard microcontroller design!)

使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮(A full adder design)

利用FPGA采集按键，加了消斗。其实跟单片机的效果差不多。-The use of FPGA collect keys, plus the elimination fighting. In fact, almost with the effect of SCM.

嵌入式的LCD的图片显示程序，是LCD最好的资料。(Embedded LCD picture display program is the best LCD data.)

这是led流水灯的vhdl描述，很好的啊-led s hdl describe

verilog full case and paralel case directive usage

说明：  是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)

this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural