基于FPGA的交通灯的设计 有Verilog HDL 源码、仿真图与引脚配置图，已下载实现...

在Altera开发板上实现RS232串口通信，平台为CycloneII，可通过QuartusII软件修改引脚移植到其它平台(Realize RS232 serial communication on Altera development board, platform for CycloneII, through software QuartusII modify pin portable to other platforms)

ENDAT 协议说明，包括时序等详细的说明，(endat Encoder characteristics)

VHDL同步串口发送部分，基于Xilinx ISE的编程平台(synchronous serial port sending part on VHDL)

电子密码锁，采用基于fpga的设计，可以设置6位密码-Electronic code locks, FPGA-based design, can be set 6 password

说明：  基于FPGA的信号发生器，产生了正弦波，方波，锯齿波和三角波四种波形，按下一次按钮，波形切换一次。按下另一个按钮，改变波形的频率(The signal generator based on FPGA can generate four kinds of waveforms: sine wave, square wave, sawtooth wave and triangle wave. Press the button once and switch the waveform once. Press another button to change the frequency of the waveform)

Verilog HDL 高级数字设计源码 _chapter4(Advanced Digital Design Verilog HDL source _chapter4)

说明：  BUS documentation and map reffereces

同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。 系统以同步信号开始连续发送四个字节，在发送中出现5个1时插入一个0，在四个数据发送结束而下一次同步没有开始之前，发送7FH，这时中间不需要插入零 -synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal system to start sending four consecutive bytes, in this emerging 5 1:00 insert a 0, at the end of four data sent and the next synchronization not started before, sending seven FH, then the middle is not inserted

cordic算法的fpga的实现 采用altera芯片-cordic realization algorithm using fpga chip altera

verilog编写的QPSK发射机的ＦＰＧＡ部分，已经过验证，完全达到要求。调制矢量误差４％(QPSK transmitter verilog prepared by the FPGA portion, has been proven, fully meet the requirements. Modulation vector error of 4 )