ahb 总线协议

1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES

如何在语言 VHDL 实现液晶显示中显示的数据转移

xillinx Spartan6 FPGA DDR 接口设计指南(xillinx Spartan6 FPGA DDR Interface Design Guidelines)

标准电视信号的同步生成程序，利用VHDL和原理图，利用Quartus综合-Standard television signal to generate the synchronization procedures, the use of VHDL and schematic diagram, using Quartus integrated

实现psk调制解调，vhdl代码，仿真文件也有(psk shixian tiaozhiyujietiao)

Advanced FPGA Design - Architecture, Implementation, and Optimization(Advanced FPGA Design- Architecture, Implementation, and Optimization)

adc0809 转换，verilog代码(adc0809 conversion, verilog code)

一个完整的设计DE2_project,希望对大家有所帮助，谢谢ok-A complete design DE2_project, everyone would like to be helpful, thank you ok

本实验是用LCD12864显示英文 显示 Our FPGA EDA NIOS II SOPC FPGA(This experiment is shown in English with LCD12864 display Our FPGA EDA NIOS II SOPC FPGA)

曼彻斯特编解码 Xilinx提供的VHDL的源代码-Manchester codec Xilinx provide VHDL source code