Triscend supports the use of the Model Technology ModelSim logic simulator for V...

基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性(Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness)

Everspin SPI MRAM chipset(MR25H10,MR25H40,MR25H256)

vhdl project at sbu uni in iran uart

rc6 algorithm designed based on verilog and is verified

使用Ｖeriolog hdl 编写手机屏测试程序．-Veriolog hdl prepared to use cell phone screen test.

对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)

PPM编码器的测试文件，可以测试PPM编码是否正确(PPM encoder test file, you can test whether the correct PPM encoding)

硬件描述语言VHDL的频率计程序,可用于做实验,或者初学者借鉴.-Hardware Description Language VHDL of the frequency counter program can be used for experiments, or the beginners learn.

采用FPGA 来实现一个基于OFDM 技术 的通信系统中的基带数据处理部分，即调制解调器。其中发射部分的调制 器包括：信道编码（Reed-Solomon 编码），交织，星座映射，FFT 和插 入循环前缀等模块。(FPGA to implement a baseband data based on OFDM technology in the communication system processing section, namely modem. Transmitter modulator includes: channel coding (Reed-Solomon coding), interleaving, constellation mapping, FFT and insert the cyclic prefix modules.)

一些较为经典的VHDL代码,专注于信号分析与检测方面-Some of the more classic of the VHDL code, focusing on signal analysis and testing