作为一个简明的教程，主要宗旨是让初学者快速地了解FPGA/SOPC（可编程片上系统）开发的流程。...

用vhdl语言编写的16bit的REG代码，以及iv，not and2，rca，fa，alu，acc，lfsr，mux21.

RapidIO：使用Avalon-ST直通接口的实现方法，可以在fpga上实现(rapidio altera)

使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public

是codic算法实现atan的C程序，包括定点和浮点程序，已经通过验证。(Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.)

说明：  这是一个单个的九层的电梯控制系统的VHDL代码，具有外部上下楼控制按钮和内部上下楼控制按钮。另外还有测试代码。(This is a design of nine floor lift control system with VHDL code and testbench.)

《Verilog HDL 程序设计教程》4-"Verilog HDL Design Guide" 4

verilog支持noise噪声的端口port, 可以用于仿真运行. 评估噪声影响 Verilog port that supports noise and can be used for simulation run. Evaluate noise effects

Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.

68013与FPGA的通信，包含了固件程序与verilog程序(68013 and FPGA communication, including firmware and verilog program)

CSS配合jquery制作完美漂亮的时钟，貌似在IE8下时钟不能获取时间啊！支持ie9、chrome、safari、firefox、opera （Chrome显示效果最佳，IE9下时钟无法工作）日历和骰子是原创，CSS3时钟并非原创但经过改良支持opera。数字日历的兼容性不错，圆形时钟就差点了，也希望一起交流，共同改进。(CSS with the jquery make perfect beautiful clock, seemingly in IE8 under the clock can not get the time ah! Support ie9, chrome, safari, firefox, opera (Chrome show the best results, the clock does not work under IE9) calendar and dice is original, CSS3 clock is not original but after improved support opera. Digital calendar compatibility is good, almost round the clock on, and also hope together, and work together to improve.)