倍频器

在altera DE2 的开发板上采集图像，到lcd显示的原程序 。-In altera DE2 development board collecting images, lcd display to the original procedure.

VerilogHDL,对初学者很有帮助的,可以一下的!-VerilogHDL, very helpful for beginners, you can look in!

K2FPGA开发板实验教程——I2C协议说明及verilog实现读写I2C器件，中文内涵代码，验证可用。(K2FPGA development board test tutorial- I2C protocol description and verilog read and write I2C devices, Chinese connotation code to verify availability.)

基于verilog的1588V2协议的fpga实现，目前项目通用代码，供大家参考(Based on verilog 1588 v2 fpga implementation of the agreement, the project general code, for your reference)

VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是51~94个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC publication, here is the 51 ~ 94 examples

mimo—ofdm线性卷积，实现输入的800位宽的数据同两个序列的卷积(Mimo- ofdm linear convolution 800 bits wide input data with the convolution of two sequences )

说明：  数字钟通过verilog实现，并且支持Modelsim仿真，通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)

Altera DE2 上使用 vhdl 语言设计 RS232 控制器。这是一个串口模块可用于嵌入系统。

231卷积码的verilog实现，前面是详细的文档说明，有源程序，绝对原创！！！！(Verilog achieve 231 convolutional code, preceded by a detailed description of the document, the source, the absolute originality! ! ! !)

此代码实现4人表决功能，4人中有三人同意即为通过。(Four voting)