JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。

PS2 Module for Altera DE2

波形发生器，带TESTBENCH， 多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn

isa MEMORY PLAN eu biu asm

正弦波UPS中的逆变电路 包括原理分析 框图 及原理图(Sine wave UPS inverter circuit the principle analysis block diagram and schematic)

VHDL开发的计数器。源程序不复杂，应该都能看懂。最重要的注意：是时序问题-VHDL development of the counter. Source code is not complicated, should be able to understand. The most important Note : Timing is the issue

vmm primer的使用使用文档，和之前vmm primer源代码配套使用！(vmm the primer use of the use of the document, and before supporting vmm the primer the source code to use!)

FIFo参考设计16x32 FIFO with simultaneous read/write operations.-FIFO design-16x32 FIFO with simultaneous read/write operations.

说明：  serdes中的8B/10B编码 verilog实现(Implementation of 8B / 10B coding Verilog)

K2FPGA开发板实验教程——I2C协议说明及verilog实现读写I2C器件，中文内涵代码，验证可用。(K2FPGA development board test tutorial- I2C protocol description and verilog read and write I2C devices, Chinese connotation code to verify availability.)

fpga永磁同步电机矢量控制系统，包括死区等模块(fpga foc)