JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。

利用Verilog HDL对AD7705进行控制ADC采样，实验室师兄的-Using Verilog HDL to the AD7705 control ADC sampling, laboratory师兄the

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine

BCD码减法实现程序，非常完整，采用Verilog HDL语言实现。(BCD subtraction to achieve program code, very complete, using Verilog HDL language.)

说明：  半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

VHDL语言编程简单实例若干，适合于初学者(VHDL language programming simple example, suitable for beginners)

该实验完成的功能是STM32与FPGA通信(The function of the experiment is STM32 and FPGA communication)

说明：  基於空間向量調變的開關法，在於載波做比較切出方波再送至開關讓馬達啟動(Based on the switching method of space vector modulation, the square wave is cut out for carrier comparison and sent to the switch to start the moto)

This is the Spartan 3E tutorial_02.

Verilog Blocking and Non Blocking

VHDL implementation using mouse and monitor