JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。

VGA字符显示VHDL程序 可以直接用于工程的设计与开发-VGA display characters can be directly used for VHDL design and development

有用的VHDL源代码-useful VHDL source code

Verilog HDL 写的SVPWM 算法的实现，使用的是altera 风暴系列的FPGA，占用资源1w+逻辑宏单元(Verilog HDL ，SVPWM)

ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(ARM7 System IP Core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)

通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)

单相混合有源电力滤波器的设计与控制，在matlab中的仿真模型，功能效果很好。(The design and control of single-phase hybrid active power filter in matlab simulation model, the function works well.)

说明：  HDMI协议的Verilog实现，通过对RGB三个通道分别进行TMDS编码完成，纯原创代码(Verilog implementation of HDMI protocol, through TMDS coding of RGB three channels, pure original code)

详细说明：基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,eccGen256Byte 文件夹为ECC 产生程序，EccErrLoc文件夹为ECC错误定位程序。

FPGA实现BPSK调制，带Modelsim仿真，实际系统测试通过，载波信号，调制波信号频率可调(FPGA implementation BPSK modulation with Modelsim simulation, the actual system test, the carrier signal, modulated wave signal frequency adjustable)

des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language