BulkIn是FPGA向CY7C68013发送数据 BulkOut是FPGA从CY7C68013接收数据,可以用LED显示...

01 线性调频信号的卷积功能测试（匹配） 02 LFM一维距离像 03 MATLAB联合FPGA仿真输入/输出功能测试 04 解速度模糊 05 扩展目标检测(01 LFM Test function of "conv" 02 LFM Range 03 MATLAB and FPGA 04 resovle speed resolution 05 Extended moving target)

This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.

设计并制作一个14键单音电子琴预先存入一些曲谱电路在4Hz的时钟控制下自动播放 通过220V电源适配器给电路提供工作电源-Design and production of a 14-key electric piano tone into a number of music scores advance in 4Hz clock circuit under the control of automatic play through 220V power adapter to provide power to the circuit

此代码包含非常有趣实现想法加密使用 vhdl 语言使用 Xilinx 的工具 ！希望你可以自定义和使用供您自己个人使用的这份工作 ！住宿已连接并且放松的感觉，要问的问题

基于FPGA的图像采集卡的设计与相关说明-FPGA-based design of frame grabbers and related note

AD9910实现脉冲内线性调频信号，仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)

用max+plusII编写的vhdl程序 乒乓球游戏机-with max plusII vhdl procedures for the preparation of the table tennis game

本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。-EDA chapter describes the two technologies integrated application design example: digital alarm clock and direct digital synthesizer DDS.

altera max10 USB demo，使用了phy，把开发板配置成U盘模式(altera max10 USB demo，using PHY device，design a U pan)

电子秒表，FPGA实现,本科某课程设计，程序注释非常详细，(FPGA TIME-COUNTING)