基于FPGA的温度计源代码，VHLL语言

针对串行存储器M25P80应用的verilog程序-M25P80 serial memory for applications Verilog program

VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子，生成的是一个定点的正弦数据表文件，需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)

用Verilog实现自动售货机功能，代码较初级。易懂，内含test文件。(Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.)

说明：  控制步进电机转动，正反转，旋转角度完美掌握。很好用，亲测(Control stepping motor rotation, positive and negative rotation, perfect control of rotation angle. Very easy to use, personal test)

eDP接口TFT-LCD显示驱动原码（verilog+c）(eDP Interface TFT-LCD display driver source code (verilog+c))

利用FPGA实现频率测试,基于VHDL实现,具有良好的测试性能可直接使用-Realize the frequency of testing the use of FPGA-based VHDL realize, has a good test performance can be directly used

说明：  SSI转ABZ信号FPGA程序，测试完全可用(Function of SSI convert to ABZ signal,is available)

说明：  此程序用来实现图像的采集和帧数的计算功能。(Image acquisition and calculation of the number of frames.)

说明：  Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA module. Includes various PTP related components for implementing systems that require precise time synchronization. Also includes full MyHDL testbench with intelligent bus cosimulation endpoints.

modsim仿真必备，可以帮助你解决很多你对软件不熟悉的问题！-Simulation modsim necessary, I can help you solve many of the software you are not familiar with the problem!