基于FPGA的温度计源代码，VHLL语言

Altera board Mp3 project

可以用于按键去抖动的电路应用，采用vhdl编写-Button can be used to jitter circuit applications, the preparation of the use of VHDL

完成GPS的IRIG_B码解码，已经模块化，并且有详细的中文注释(Completed the GPS IRIG_B of decoding modular, and there are detailed notes in Chinese)

利用VHDL语言编写的4*4键盘扫描程序，经过测试，可以放心使用。(Using VHDL language 4* 4 keyboard scanning procedures, tested, safe to use.)

本文参考了Xilinx 官方文档UG873，“System Design Using Processing System High Performance Slave Port”。主要实现了PL 中AXI CDMA IP 与PS 部分HP64bit 从接口集成。 本例中AXI CDMA 部分扮演主机，从PS 部分DDR 系统内存中源缓冲区拷贝一列数据到目 的缓冲区。可以分别采用裸机工程和基于Linux 的应用软件来实现功能。(This reference to the official document Xilinx UG873, " System Design Using Processing System High Performance Slave Port" . The main achievement of the PL in AXI CDMA IP interface integration with PS part HP64bit. In this example AXI CDMA part to play host, a copy of a column of data into the destination buffer section PS source DDR system memory buffer. Can respectively bare engineering and Linux-based applications to achieve functional.)

基本逻辑门电路的设计方法，或门的VHDL的设计让你更容易步入VHDL的设计氛围中，简单的或门编制-Basic logic gate circuit design methods, or the door of the VHDL design allows you to more easily into the VHDL design environment, the simple OR gate preparation

一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation

在Quartus中，利用FPGA例化的存储器实现程序的BOOTLOADER的搬移(In Quartus, the use of FPGA case of memory to achieve the program' s move BOOTLOADER)

design ram v8051 for project

Arbiter code for simulation purpose