verilog spi file with testbench

Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl

说明：  FPGA程序的top.v文件，主要实现DDS信号发生器功能，通过定时器，可简单实现输出幅值无极跳变(FPGA procedures top.v documents, the main function of DDS signal generator, through the timer can be simple to achieve the output amplitude wuji hopping)

说明：  本设计是基于FPGA的高速并行接口通信接口和协议设计，该设计使用的是8 位并行接口，通过配置FPGA的FIFO寄存器保证了在高速并行下的数据稳定性，在 最终的测试中，该协议能够稳定传输的速度为80Mbps。(This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8 Bit parallel interface ensures the data stability under high-speed parallel by configuring the FIFO register of FPGA. In the final test, the protocol can stably transmit at 80 Mbps.)

说明：  一个完整的雷达系统仿真MATLAB程序，非常具有参考价值(A complete radar system simulation MATLAB programs have great reference value)

IEEE Standard VHDL language

SDIO 接口，实现SD卡的控制器功能，带有详细的注释(SDIO Interface,to realize the controller of SD Card,and have detail description.)

it is a new describng system for it field

使用Xilinx3S400开发的钢板检测算法中心化算法，通过测试。-a vhdl-program use Xilinx3S400

---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbone_BFM project ---- ---- http://www.opencores.org/cores/Wishbone_BFM/ ---- ---- ---- ---- Description ---- ---- Implementation of Wishbone_BFM IP core according to ---- ---- Wishbone_BFM IP core specification document.--------- ---- WISHBONE Wishbone_BFM IP Core---- -------- ---- This file is part of the Wishbone_BFM project---- ---- http://www.opencores.org/cores/Wishbone_BFM/---- -------- ---- Description---- ---- Implementation of Wishbone_BFM IP core according to---- ---- Wishbone_BFM IP core specification document.

具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.