verilog spi file with testbench

基二8点fftverilog实现。经过modelsim仿真通过(Base 2 fftverilog implementation at 8 o clock. Go through the modelsim simulation)

CMV2000的对齐模块，适用于其他对齐模块，自行修改(CMV2000 alignment module, suitable for other alignment modules, self-modifying)

Bayer 转RGB Verilog代码实现。。5*5 窗口。在工程中应用的(Bayer to RGB Verilog code implementation. 5*5 window. Applied in Engineering)

几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code

一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合-FIFO realize a new method, verilog description, modelsim 6.0 through simulation, Quartue integrated

可供初学者学习 比较简单 一读就能明白 LED7数码显示程序(Relatively simple for beginners to learn the first reading of the digital display program will be able to understand LED7)

由乘法器组成 单边带信号产生的 仿真源代码 msm (Composed of single sideband signal by the multiplier generated simulation source code msm)

fpga的按键程序，实现按键和led的对应点亮。(The key program of FPGA realizes the corresponding lighting between keys and led.)

数字脉冲宽度调制，将输入的数字信号转换为对应占空比的模拟波形(Digital pulse width modulation, the digital signal is converted to the corresponding input of the duty cycle of the analog waveform)

基于fpga和dsp架构的gps接收机的设计和实现(Design and Implementation of gps Receiver Based on fpga)