verilog spi file with testbench

QPSK调制下的（5,7）卷积码的编码和维特比译码与BPSK调制下（5,7）卷积码的编码和维特比译码的BER特性(QPSK modulation under (5,7) convolutional code encoding and Viterbi decoding and BPSK modulation (5,7) convolutional code encoding and Viterbi BER characteristic)

CMV2000的对齐模块，适用于其他对齐模块，自行修改(CMV2000 alignment module, suitable for other alignment modules, self-modifying)

FPGA 数码管接口例化编程，学习初级入门verilog编程技术(FPGA 数码管接口例化编程)

利用Quartus 综合简单的计时器功能，欢迎大家下载、参考。谢谢大家的支持！

控制器灯具有线和无线控制器采用STC11F02做的(Controller for lamp wired and wireless controller using STC11F02 to do)

64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核(64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS)

mico8  vhdl  project lattice出的小资源mcu 256luts  值得学习

可以实现DDS 的正负线性扫频以及在线参数设置(DDS ad9914/ad9915 code)

msk的verilog程序 利用ＦＰＧＡ实现-MSK procedures for the use of Verilog FPGA realize

说明：  参照can芯片 saj1000控制器结构，写的can控制器(According to the structure of can chip saj1000 controller, the CAN controller is written)