8位乘法器的VHDL代码

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以GPS为时间基准，实现多传感器器数据同步采集，整合信息后发送 VERILOG语言编写 QUARTUS II环境(GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II)

说明：  LTE is an abbreviation for Long Term Evolution.

fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh

在vivado开发环境下，调用ram IP，实现可调频的正弦波信号发生器。(vivado IP signal generator)

实现LDVS接口数据接收 含有协议结构以及处理(lvds Verilog 512 frame)

VHDL黄金版，本人费了九牛才找到，帮助初学者入门-VHDL version, I spent nine cattle to find help beginners entry

可编程器件厂商Altera出品的8b10b编码器源代码(Giga8b10b v10)

如果需要用verilog设计一项比较简单的功能，那么这个浅显易懂的程序能让你很快明白点阵的设计方法，尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)

basic verilog for students