多进制数字频率调制(MFSK)系统VHDL程序

ALTERA关于CCD的一些verilog程序，都通过运行无误的。-ALTERA on a number of Verilog CCD procedures, both by running unmistakable.

ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules

用fpga制作一个音乐播放器，此为浙江大学信电系fpga教程大实验成果。(Use fpga make a music player, this is the letter Electrical Zhejiang University fpga tutorial big experiment results.)

用Verilog编写的以太网控制器，可以使用，里面是全部verilog源码(Ethernet controller based on Verilog, can be used directly, all verilog files)

多倍（次）分频器 请注意: 本例的各个源描述的编译顺序应该是: 52_divider.vhd 52_divider_stim.vhd-Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd

脉冲多普勒雷达回波信号相干积累的VHDL源程序-pulse Doppler radar echo signal coherent accumulation of VHDL source

基于FPGA的希尔伯特变化的verilog代码(Hilbert change verilog code)

verilog编写的数字信号发生器NCO用CORDIC方法实现产生sin cos信号，流水线结构，简单实用。(verilog prepared by the digital signal generator NCO using CORDIC method implementation generate sin cos signal, pipelined architecture, simple and practical。)

基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine