多进制数字频率调制(MFSK)系统VHDL程序

使用LPM_ROM的实际的例子-Use of practical examples LPM_ROM

The description header can be found in signal_processing_library.h.

PCIe数据链路层的协议详解，对做PCIe接口有非常重要的指导价值。(PCIe data link layer protocol detailed, do PCIe interface very important value.)

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE(Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE)

描述了使用FPGA接口PDIUSBD12开发USB接口的流程.-Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.

这是个UART发送的VHDL程序，调试过，还可以-This is a UART to send the VHDL program, debug, and can also be

A Dec example written in VHDL.

AMBE2000的压缩数据输出输入的Verilog代码，实现了自回环（loopback）效果. 希望对学习verilog语言的同学有所帮助。(The Verilog code of AMBE2000. input and output of compressed data to achieve a self-loop (loopback) effect. hope to help the one who is studying the verilog language.)

方案组成模块及系统框图 本方案设计主要由以下模块组成 1：顶层模块 2：数据输入排序模块 3：系统控制模块 4：RAM控制器模块 5：ROM控制器模块 6：蝶型单元模块(Program composition module and system diagram The design of this scheme is mainly composed of the following modules 1: top module 2: data input sorting module 3: system control module 4:RAM controller module 5:ROM controller module 6: butterfly type unit module)

联邦滤波法，毕设时写的，可以和其他方法的做比较(Kalman filter, write the complete set up, and other methods to compare)