多进制数字频率调制(MFSK)系统VHDL程序

说明：  串口通信通用模块，FPGA Verilog语言 ise，vivado环境(uart,FPGA Verilog, ise,vivado)

能够成功的实现走马灯功能，使LED循环亮灭(To succeed the implementation of the version function, make the LED circular light out)

MPEG-2TS 流嵌入控制数据的设计，设计的要求是用控制数据替换MPEG-2 TS 流中的空帧-MPEG-2TS control data stream embedded in the design, the design requirements is to control data to replace MPEG-2 TS stream of the air frame

说明：  实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)

VHDL源代码包-VHDL source code

this program is a simulation for Aloha

全自动洗衣机的控制器。 1.洗衣机的工作步骤为洗衣、漂洗和脱水三个过程，工作时间分别为：洗涤10秒，漂洗5秒，脱水5秒； 2.用一个按键实现洗衣程序的手动选择：A、单洗涤；B、单漂洗；C、单脱水；D、漂洗和脱水；E、洗涤、漂洗和脱水全过程； 3.用显示器件显示洗衣机的工作状态（洗衣、漂洗和脱水），并倒计时显示每个状态的工作时间，全部过程结束后，应提示使用者； 4.用一个按键实现暂停洗衣和继续洗衣的控制，暂停后继续洗衣应回到暂停之前保留的状态； (Automatic washing machine controller. 1 washing machine work steps for the laundry, rinsing and dehydration three processes, working hours are as follows: washed for 10 seconds, rinse for 5 seconds, dehydrated five seconds 2 with a button to manually select the program to achieve laundry: A, single-washing B, single rinse C, a single dehydration D, rinsing and dehydration E, washing, rinsing and dehydration the whole process 3 with a display device display the working status of washing machine (laundry, rinsing and dehydration), and each state countdown show working hours, after the whole process should prompt the user 4 laundry with a button to pause and continue control of laundry, laundry should be back after a pause pause before continuing to retain the state )

篮球24s计时器，元器件简单，功能复杂。满足小型计时需要。

uart通信的Verilog实现,包含rx tx 以及testbench(Verilog implemention of UART telecommunicate)

verilog code for bus controller