多进制数字频率调制(MFSK)系统VHDL程序

100个VHDL的例子-100 examples of VHDL

用AHDL语言编写,MAXPULS开发.通信不受外部时钟速率和数据字节数目限制.-with AHDL prepared MAXPULS development. Communications from external clock rate and restriction on the number of data bytes.

有一个 8 位全加器 VHDL 代码。我测试该代码在协同，看到了这段代码的工作。

说明：  生成一个M伪随机序列码，在ISE平台上可跑通(Generate an M Pseudo-Random Sequence Code which runs on ISE platform)

verilog源代码，实现两种方法的模3运算。(verilog source code，to implement the calculation of mod-3 by two means.)

FPGA控制SRAM读写时序源码，代码桂发，新手一看就懂(FPGA control SRAM write timing source code Guifa novice understand at a glance)

ACO-OFDM sdakldjas seuekdsjakdnskd

PID控制器的verilog实现，做闭环控制器的人可以参考(PID controller verilog implementation of closed-loop controller may make reference to)

开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit

8051内核的hdl代码，实际上是verilog格式不过上载页面只有一个vhdl选择，值得一读， 里面对仿真和验证的说明很有含金量-the hdl code of 8051 core