自动打铃系统 附带时钟 定时打铃 整点打铃

32位扰码器的verilog代码，编译通过(The Verilog code of 32_bit scrambler)

有很多例子及测试代码，对初学者很有帮助，很容易上手-a lot of examples and test code, useful for beginners, it is easy to get started

基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)

说明：  XC7A35TCSG324-1的Verilog频率计程序，支持十分频，支持切换内外信号输入(Verilog frequency meter program of xc7a35tcsg324-1 supports decadal frequency division and switching internal and external signal input)

说明：  很好的免费学些 verilog教程 欢迎下载(Learn a good free download verilog tutorials welcome)

基于FPGA的交通灯的设计 有Verilog HDL 源码、仿真图与引脚配置图，已下载实现 -FPGA-based design of traffic lights have Verilog HDL source code, simulation map with pin configuration map has been downloaded realize

最大最小值寻找程序，可以实现自动查找最大值与最小值(min_max_finder)

说明：  KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。(Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment for the Quartus II 8.0 Web Edition.)

说明：  FPGA 学习实例 动态时钟、面积、速度优化相关代码(Codes related to dynamic clock, area and speed optimization for learning examples of FPGA)

Quartus环境下多路选择器的编写代码，适合初学数字逻辑设计的进行学习(MUX in Quartus)