自动打铃系统 附带时钟 定时打铃 整点打铃

sequenceur,该模块的主要功能是，控制器，在基本的risc架构中，实现各个模块的控制-sequenceur，control

FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进行综合-FIFO procedures have been in the Verilog in ModelSim compiler and can be passed through the integrated DC

不同方法实现的CPU系统。同样支持加减乘，逻辑/算术移位，与或非等建议指令。(Different methods to achieve CPU system. Also supports, subtraction, multiplication, logic/arithmetic shift, and the like or recommend instruction.)

DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme-DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.

个人参与的某国家工程并行排序MATLAB程序，用于FPGA的RTLAB仿真，使用Simulink工具生成HDL代码。测试可用。(Individuals involved in sort of a national engineering parallel MATLAB programs for the FPGA RTLAB simulation, using the Simulink tool to generate HDL code. Test available.)

成为真正的网页制作的高手的话,必须了解并使用DHTML.这里提供了最好的手册和文档.-become truly a master pages, then have to understand and use DHTML. Here to provide the best manuals and documents.

Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs

通过用vivado完成一个流水灯项目手把手教你如何使用vivado，内容十分详细。(Using vivado to complete a running light project, you can learn how to use vivado by hand. The content is very detailed.)

fpga code for pong game

基于VHDL语言的串口发送和接收程序,自己调试通过，并已经运用在工程中(Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project)