Xilinx ISE 8.2i s license

i2c master ip for altera nios, add in qsys

A counter that starts from 0 and increments mod 16 on each rising edge of the clock

基于EDA技术设计4位十进制数字频率计的系统方案-Based on EDA technology design four decimal system solutions Cymometer

直流电机控制器，属于精品vhdl源码，可在eda仿真工具上仿真实现-DC motor controller is excellent VHDL source code can be sown in simulation tools Simulation

manchester_verilog源代码(manchester_verilog source code)

本程序实现不同频率时钟的产生及其相互转化-this program different clock frequencies to the formation and transformation

（1）MTI （2）用FFT实现MTD （3）用FIR滤波器实现MTD ((1) MTI (2) using FFT realization MTD (3) with the FIR filter implementation MTD)

FPGA开发超声波测距，可改写工业探伤或倒车测距等系统，quartus2下选择EP2C5Q208C8（CycloneⅡ） 支持目前淘宝上能买到的所有4-5针超声波模块 应用cycloneⅡ自带除法模块 开发板为有光技术YG2.1 生成电路规模较小 ！！注意：移植程序仅需重新约束数码管和超声波模块的针脚 (Ultrasonic Ranging FPGA development, industrial inspection or reverse rewritable ranging systems, EP2C5Q208C8 (CycloneⅡ) under quartus2 4-5 needle ultrasonic module supports all currently scouring the treasure can buy Applications cycloneⅡ own division module Development board bright technical YG2.1 Small scale generating circuit ! ! Note: The migration program only re-constraint digital and ultrasonic modules Pin)

基于FPGA的CPU核及其虚拟平台的设计与实现-FPGA-based CPU core and its virtual platform design and implementation of

ieee paper on power gating and can be use full for implementing on ip core