Xilinx ISE 8.2i s license

这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!-This is my learning process in the middle of the 10-minute program, containing various clock module and the counter, accumulator, and can download, compile!

说明：  verilog开发的经典教材，详细介绍了语法，常见历程，以及通用的程序段(verilog development of the classic materials, detailed information on syntax, common history, as well as the common program segment)

开发工具是quartus II 7.0以上版本，这是一个verilog语言的分频器设计，个人作业设计，供参考学习(verilog，quartus II 7.0)

dds数字移相信号发生器,功能齐全通过验证-dds digital shift Signal Generator, full-featured validated

files describe how to configure an ADV7180

FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。(FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.)

basic verilog for students

说明：  内附几十种小程序，有状态机、比较器、波形发生器、乘法器、加法器、步进电机控制器等，希望大家能用的上。(Containing dozens of small programs, for reference，This is about FPGA,a tool ,we can study,but in ourselves.)

基于fpga的电子血压计。pdf文档，好用，内容清楚简单，转载而来(Electronic sphygmomanometer based on fpga)

这是用VHDL编写的译码程序,程序简单易懂-VHDL prepared decoding procedures that are simple to understand