Xilinx ISE 8.2i s license

HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)

异步串行传输的verilog hdl 功能文件以及测试文件(The verilog hdl source and the testbench of asynchronous serial transmission )

cpu与GPU协同计算一个同时支持GPU与CPU的MapReduce框架实现(cpu and GPU collaborative computing)

通过FPGA实现整数阶混沌系统，通过定点数的方式，全并行。(The realization of integer order chaotic systems through FPGA)

对pci9054芯片的配置进行了设置，并对PCI9054的各状态机进行了设置，程序经过了测试(Pci9054 chip on the configuration of the set, and each state machine PCI9054 been set, the program have been tested)

IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY

FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。(FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.)

this is a vhdl program...

用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware description language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.

在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)