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Electronic and system matlab simulation
Electronic and system matlab simulation
- 2023-07-05 12:50:04下载
- 积分:1
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IIR-FPGA
基于FPGA实现IIR滤波器的程序,用VERILOG编程语言实现(The program based on the FPGA implementation of the IIR filter is implemented in the VERILOG programming language)
- 2017-05-24 11:08:15下载
- 积分:1
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chuankou
本实验为UART回环实例,实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx,以及时钟产生模块clk_div。uart_rx将收到的包解析出8位的数据,再传送给 uart_tx发出,形成回环。参考时钟频率为100MHz,波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分:1
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HOWTO_-Get-Configuration-and-Location-Information
this document used for how to get config and location information of PCI card
- 2012-07-21 12:26:16下载
- 积分:1
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this a spartan 3E base project file.
this is the project of game in which vga...
this a spartan 3E base project file.
this is the project of game in which vga is interfaced to FPGA.
this file is main file in which vga timing is maintained.-this is a spartan 3E base project file.
this is the project of game in which vga is interfaced to FPGA.
this file is main file in which vga timing is maintained.
- 2023-07-29 01:40:03下载
- 积分:1
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VGA_Display(FPGA)
在FPGA开发平台上,通过按键控制一个弹球小游戏。输出VGA显示信号输送到显示器上显示(On the FPGA development platform button control of a pinball game. VGA output signal is supplied to the display displayed on the display)
- 2017-05-02 10:59:42下载
- 积分:1
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Cadence VHDL Operational the package, seeking to achieve root, You are not squar...
Cadence的VHDL运算库包,实现求方根,平方你是不是以前不知道怎么弄.哈哈.-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.
- 2022-08-16 03:35:39下载
- 积分:1
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Low
低通滤波器在QUARTUS7.0开发环境下的文本与框图结合的实现方法的源代码-Low-pass filter QUARTUS7.0 development environment in the text and diagram combination of methods to achieve source code
- 2022-11-29 01:15:03下载
- 积分:1
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VC707_MIG_DDR3
说明: VC707_MIG_DDR3.sim文件夹中是仿真的文件:testbench和DDR3模型参数
VC707_MIG_DDR3.srcs文件夹中是源文件,包含DDR3的控制、收发模块、顶层文件(VC707_ MIG_ In ddr3.sim folder are simulation files: testbench and DDR3 model parameters
VC707_ MIG_ Ddr3.srcs folder is the source file, including DDR3 control, transceiver module, top-level file)
- 2020-10-16 19:20:53下载
- 积分:1
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Desktop4
combinational circuits code in vhdl
- 2018-08-13 17:33:14下载
- 积分:1