编译实现循环码的产生，用FOR循环分别对其中的码元进行设置。...

16点FFT，简单易理解，适合初学者了解(16 point FFT, simple and easy to understand, suitable for beginners to understand)

quartus ii 环境下，一个完整的利用TEXTIO仿真的源代码，包括读数据文件和输出数据到文件。(Under quartus ii environment, a complete simulation using TEXTIO source code, including reading data files and output data to a file.)

该部分的主要功能是完成基于FPGA的polar码编码。(The main function of this part is to complete the FPGA-based polar code coding.)

说明：  一个简单的键盘接口模块程序，对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)

Verilog代码，支持IO，中断的cpu实现。(Verilog code, support IO, interrupt cpu implementation.)

坦克游戏用VHDL语言编写。Altera的随身携带套件DE1。PS2键盘接口和VGA

sub opercore USB CRC5 and CRC16 Modules //// //// //// //// //// //// Author: Rudolf Usselmann //// //// rudi@asics.ws //// //// //// //// //// //// Downloaded from: http://www.opencores.org/cores/usb/(sub opercore USB CRC5 and CRC16 Modules//////////////////////// Author: Rudolf Usselmann//////// rudi@asics.ws//////////////////////// Downloaded from: http://www.opencores.org/cores/usb/)

一种基于FPGA的CPU设计-FPGA-based CPU design ........

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第三个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The third document

实现一个循环冗余码,是老师给的例子，别的同学已经验证-a cycle ruduandency code