编译实现循环码的产生，用FOR循环分别对其中的码元进行设置。...

使用matlab实现cdma 系统的rake接收机，比较最大比合并，等增益合并和选择性合并接收算法的性能(脢 鹿 脫脙matlab脢渭脧脰cdma 脧渭脥 鲁 渭脛rake 陆 脫脢脮 禄煤 拢 卢 卤 脠 陆 脧 脳 卯)

适应多个模式的rs编码，Verilog，选择对应的多项式(RS coding adapted to multiple modes.)

Great guide for writing VHDL

说明：  一篇关于LDPC解码算法的FPGA用VHDL实现的PDF文件，老外写的，还可以，可以参考，欢迎大家下载！(A PDF about the FPGA implementation of LDPC algorithm, written by foreigners, but also, you can refer to, welcome to download!)

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选，12小时制时有上下午指示；当计时到预定时间（此时间可手动设置）时，扬声器发出闹铃信号，闹铃时间为10秒，可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely.

Verilog 我认为写的非常好的细节书(Verilog In my opinion written details of the book)

以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)

高速FIFO，verilog设计。速度高达130Mhz(High-speed FIFO, verilog design. Speed up to 130MHz)

verilog jtag源码及原理，还有debug模块。边界扫描等(verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.)

the interface design of pcie based on FPGA