VHDL项目设置：FLV

在quartus平台下，并使用verillog hdl编写的时钟分频仿真(In quartus platform and use verillog hdl write clock divider simulation)

这个程序为通信中的16QAM调制程序，可用于无线或有线通信系统的调制仿真之用。(The 16QAM modulation communication this program can be used for wireless or wired communication system modulation simulation purposes.)

用FPGA实现SPWM波输出，其中包含三角波和正弦波(With the FPGA realization of SPWM wave output, including triangle wave and sine wave )

用例化语句和case语句编写的全加器的VHDL描述。-Of statements were prepared using the full adder of the VHDL description.

说明：  FPGA接收串口UART发来的指令设定温度报警值，实时采集DS18B20温度传感器并显示，带报警功能(FPGA receives the instruction from UART, sets the temperature alarm value, collects and displays DS18B20 temperature sensor in real time, with alarm function)

设计制作一个可容纳4组参赛者的数字智力抢答器，每组设置一个抢答按键； 电路具有一第一抢答信号的鉴别和锁存的功能。在主持人将系统复位并发出抢答指令后，若参加者按抢答键，则该组指示灯亮并用组别显示抢答者的组别。此时，电路具有自锁功能，使别组的抢答开关不起作用。 设置计分电路。每组在开始时预置成6分，抢答后主持人计分，答对一次加1分。(The design can accommodate a the Entrants digital intellectual Responder, each set answer in a key circuit has a first answer in the signal to identify and latch functions. Host to the system reset and sent the answer in instruction, participants answer in key, the group of the group light and display the answer in the group. At this point, the circuit has a self-locking function does not work in other groups to answer switch. Set Scoring circuit. Preset six points each at the beginning of the answer in scoring after the host, answer time, add 1 point.)

电子设计大赛作品_音频信号分析仪的FPGA源码(一等奖)-Electronic Design Competition works _ audio signal source analyzer FPGA (first prize)

四轴动力模块，用一个顶模块控制，输入有：油门（20档）；指令；水平仪控制指令，4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)

it is hybrid squarer circuit which will be designed using reversible gates which having les hardware complexity with compared to the conventional gates

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