FFT processor design and applied research, suitable for signal processing fpga t...

实现了四bit计数器的功能，使用的是VHDL语言描述(Four-bit counter, using the VHDL language description)

高速流水的SDRAM控制器，最高速度可达速度在200M左右(high speed SDRAM controller)

TCM编码的调制端，采用8PSK，2/3码率的卷积码的matlab程序(TCM coded modulation client, using 8PSK, 2/3 code rate of convolutional codes of matlab program)

基于altera系列芯片lvds接口的fpga设计 verilog源码-Series altera-based chip interface lvds source fpga design verilog

利用FPGA来采集美新加速度计的数据，并将FPGA采集到的数据传给ARM系统处理-The use of FPGA to collect the new U.S. accelerometer data and the data collected FPGA passed ARM system processing

说明：  本文设计了基于FPGA的，用verilog HDL语言描述的在伽罗华域GF（ ）上的RS（6,4）编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述，然后在软件上进行编译、仿真，最终实现RS（6,4）编码，下载之后用chipscope采集数据，分析符合仿真结果，达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS (6,4) encoder. Using the ISE software Verilog HDL language for each module is described, and then compile, simulation in software, the ultimate realization of the RS (6,4) encoding, after downloading by chipscope data acquisition, the analysis with the simulation results meet the design requirements.)

这是用VHDL编写的译码程序,程序简单易懂-VHDL prepared decoding procedures that are simple to understand

VHDL_COUNTING 0_9_LED 7 段 (ĐẾM 0 ĐẾN 9 HIỂN THỊ LED 7 ĐOẠN BẰNG NGÔN NGỮ VHDL)

verilog lcd2864 适合初学者(verilog lcd2864 )

忆阻器的SPICE建模模型说明及仿真结果说明(Memristor SPICE modeling and simulation results show that the model describes)