FFT processor design and applied research, suitable for signal processing fpga t...

Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB-Xilinx, Altera, ARM, AVR, S52, Lattice series FPGA download cable circuit diagram and PCB

用vhdl语言编写的程序，可以播放乐曲，有分频模块，可播放梁祝等歌曲。

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1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES

采用CORDIC算法的直接数字频率合成器的设计(CORDIC algorithm uses direct digital frequency synthesizer design)

实现fpga上交通灯的设计，可以在开发板上实现红绿灯(Design of traffic lights on FPGA)

ahb to apb master verification

Simulation and Synthesis Techniques for Asynchronous FIFO Design

it is a filter contract VHDL .(it is a filter contract VHDL.)

利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发 时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count )