这是关于赢vhdl语言变得信号采集卡，很有实用性，大家可以来看看的。...

Viterbi译码器的编解码器的设计 用Verilog实现-Viterbi decoder。Verilog

这是“状态机设计（讲稿）”，希望对正在学VHDL的同学有帮助，谢谢！-This is the "state machine design (the script)", and I hope to learn VHDL is there to help the students, thank you!

说明：  Implementation of CORDIC atan block in VHDL

无SDRAM的PCI采集,给出PCI采集的FPGA程序，桥芯片也为PLX9054，已验证通过(No SDRAM, PCI capture, given FPGA PCI acquisition program, bridge chips for PLX9054, has been verified by)

verilog源代码，实现两种方法的模3运算。(verilog source code，to implement the calculation of mod-3 by two means.)

Xilinx fpga 设计培训中文教程,比较好的学习FPGA入门的教程(Xilinx fpga design training for Chinese curricula, better start learning FPGA Tutorial)

自己编写的红外解码子程序，但CPU资源占用较高，作教学示范用途。(prepared their infrared decoding routines, but higher occupancy CPU resources for teaching demonstration purposes.)

VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)

用VHDL语言来实现一个电子时钟，可以调时间。小时，分，秒。可以下载到实验箱来运行验证。-use VHDL to achieve an electronic clock, the time can be set aside. Hours, minutes and seconds. Experiments can be downloaded to the box to run test.

基于DE2-70开发板的VGA接口实现程序，可在VGA屏幕上显示800*600分辨率的图像，刷新频率60Hz