基于DE2-70开发板的VGA接口实现程序

可编程逻辑器件cpld与单片机双向通信的源程序-Programmable logic device CPLD and MCU for two-way communication of the source

verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，7-8章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 7- 8

verilog code for apb to ahb convert

16： 00 FFT VHDL源代码，xFFT16快速傅立叶变换（FFT）核心计算16点复数FFT。输入数据是16个复数值的向量，表示为16位2s补码-16位表示一个数据的实部和虚部。

同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated

自动计算fir滤波器系数的工具，不妨一试(Automatic calculation of filter coefficients fir tools, try)

this is "AND" gate implementation in VHDL

papers based on distributed arithmetic.

小波分析wave analysiswave analysiswave analysis(wave analysiswave analysis)

cpld/fpga积分梳状滤波器(CIC)设计-cpld/fpga Integral comb filter (CIC) design