-
01_rtc_ds1302
说明: 实现基于黑金开发板的实时时钟功能,显示时分秒(Realize the real-time clock function based on black gold development board, display time, minute and second)
- 2021-01-11 14:40:12下载
- 积分:1
-
sram
FPGA控制SRAM读写时序源码,代码桂发,新手一看就懂(FPGA control SRAM write timing source code Guifa novice understand at a glance)
- 2020-06-30 03:00:01下载
- 积分:1
-
fpga_dsp_simple
dsp和fpag通信的测试程序,包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)
- 2013-04-14 15:17:20下载
- 积分:1
-
8086
8086微机原理实验:8251串行接口、8253计数器、数码管、跑马灯。汇编语言。(8086 microcomputer principle experiment: 8251 serial interface, the 8253 counter, digital tube, Marquee. Assembly language.)
- 2013-03-15 11:07:19下载
- 积分:1
-
the transmitter and receiver modules for serial communication
the transmitter and receiver modules for serial communication
- 2022-07-22 02:02:39下载
- 积分:1
-
ofdm_integration
整合的OFDM调制解调方法,matlab文件,modelsim仿真(Integration OFDM modulation and demodulation method, matlab file, modelsim simulation)
- 2012-09-03 17:13:35下载
- 积分:1
-
ALTERA 的关于对SDRAM控制器操作的verilog相关程序,很不错绝对值得借鉴。...
ALTERA 的关于对SDRAM控制器操作的verilog相关程序,很不错绝对值得借鉴。-ALTERA on the operation of the SDRAM controller Verilog procedures, it is definitely worth a good draw.
- 2022-01-26 03:51:39下载
- 积分:1
-
本代码介绍了使用VHDL开发FPGA的一般流程,最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL,在软件开发平台ISE上完成,可以...
本代码介绍了使用VHDL开发FPGA的一般流程,最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL,在软件开发平台ISE上完成,可以在较高速时钟频率(100MHz)下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真,并完成了综合布局布线,最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
- 2022-10-09 05:15:03下载
- 积分:1
-
verilog
说明: i2c module,有i2c主机和从机模块(i2c module verilog VHDL base on i2c protocol)
- 2020-10-26 08:27:29下载
- 积分:1
-
altera的ip核,在sopcbuilder中添加后,在niosII IDE中可以用一条语句实现,音频解码的输出。...
altera的ip核,在sopcbuilder中添加后,在niosII IDE中可以用一条语句实现,音频解码的输出。-altera
- 2022-03-05 12:43:51下载
- 积分:1