基于DE2-70开发板的VGA接口实现程序

verilog分频器～时钟为50hmz，波特率采用9600bps～-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~

软件环境：TI的zstack协议栈 硬件：CC2530无线单片机 功能：利用超声波模块实现测距（该模块型号：HC-SR04 在淘宝上非常常见） 可测2厘米到3米距离(Software environment: TI' s zstack protocol stack hardware: CC2530 wireless microcontroller features: use of ultrasonic ranging module (the module Model: HC-SR04 on Taobao very common) can be measured 2 cm to 3 meters)

vhdl code for register and detemines how register works -vhdl code for register and detemines how register works

自己写的 AXI master code(AXI master code)

Multiplexer styles in VHDL

使用ALTERA的FPGA控制SDRAM的verilog程序(Use ALTERA s FPGA to control SDRAM s verilog program)

Block LU decompostion of a matrix

设计题目：基于MATLAB的FFT算法的设计 设计内容： 所设计的FFT算法应完成以下功能： （1）在MATLAB环境下编写FFT算法（不调用系统现有函数）； （2）实现对选定图片进行FFT计算、还原（IFFT计算），并与系统FFT函数做对比，进行分析； （3）设计GUI界面。 (Design topics: content based on the the MATLAB FFT algorithm design design: the design of the FFT algorithm should perform the following functions: (1) the FFT algorithm written in MATLAB environment (do not call existing function of the system) (2) to achieve the selected picture for FFT calculation, restore (IFFT calculation) system FFT function analysis (3) design GUI interface.)

it shows bcd counter

CAN驱动器MCP2515驱动，verilog编写，实测可用(CAN driver MCP2515 driver, Verilog written, measured available)