用VHDL语言来实现一个电子时钟，可以调时间。小时，分，秒。可以下载到实验箱来运行验证。...

本模块是实现格雷码和二进制码的转换，并给出仿真测试文件(This module is to achieve the conversion of Gray code and binary code, and give the simulation test file)

利用VHDL语言实现PID控制,已经过调试验证。(Using VHDL language to implement PID control)

用状态机实现密码锁State machine used to achieve code lock-State machine used to achieve code lock

Once the FPGA is located, the rest of the mapping data for the other components can be determined dynamically its section mapping registers.

matlab file for image contrast..

Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave

六个数码码动态扫描接口程序，用VERILOG语言编写的-Six digital code dynamic scan interface program, using Verilog language

使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮(A full adder design)

电子表，实现计时记分计秒的功能，同时可以对时分秒进行校正，实现调时功能。-Electronic watches, time points of dollars to achieve a second function, at the same time when the minutes and seconds can be calibrated to achieve when the transfer function.

说明：  Matlab源程序，包括插值计算、积分微分等。(Matlab source code, including the interpolation calculations, differential and so on.)