FPGA TRACKING SYS

EDK tutorial 1 ----------------

here is a VHDL example

在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令(Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions)

由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)

RAM存储器： 设定16 个8 位存储单元。如果read= 1 则dataout

用fpga驱动lcd的原代码，是用vhdl语言实现的-drive lcd by fpga，the source program is written by vhdl

Service Manual LG TV LCD DISPLAY models 2011

MPEG-2TS 流嵌入控制数据的设计，设计的要求是用控制数据替换MPEG-2 TS 流中的空帧-MPEG-2TS control data stream embedded in the design, the design requirements is to control data to replace MPEG-2 TS stream of the air frame

本程序是用vhdl开发的实现并串转换功能的程序。(This procedure is developed using VHDL implementation and string conversion function of the program.)

说明：  QUARTUS2 16.9 VHDL FPGA ENDAT2.2