FPGA在直流电机调速中的应用,利用fpga进行PID闭环控制(tell us speed control for DC motor by FPGA,use fpga for PID circle control)

反应速度测试小游戏，最小外设cpld游戏，带设计说明书(Reaction speed test games, the minimum peripheral cpld game, with design specifications)

实现basys3板子的串口通信，内容非常纤细，还带有数码管显示(Realization of serial communication of basys3 board)

说明：  altera发布的开源8b10b源代码，vhdl语言描述(altera released the source code open source 8b10b, vhdl language description)

VerilogHDL课件，老师现在正拿这个上课-VerilogHDL courseware, teachers are now using this class

 交通灯控制器控制红（r）、绿（g）、黄（y）三种不同颜色的交通灯，这三种不同颜色灯的亮、灭分别由三个定时器（timer1、timer2、timer3）控制；  当某个定时器工作时，它所控制的交通灯亮，直到设定的定时时间到（该定时器状态由’0’变’1’），交通灯跳转到另一种状态；  clk是脉冲控制端（图中未标出）；reset是异步复位端，复位状态为红色交通灯亮；  输出端r、g、y分别表示三种颜色交通灯的亮、灭状态。 ( traffic light controller control red (R), green (g), yellow (y) three different colors of traffic lights, three different colors of bright lights, off by three timer (Timer1, Timer2, Timer3 ) control  When a timer work, it controls the traffic lights, until the set timing (the timer status ' 0 ' for ' 1' ), traffic lights Jump to another state  clk is the pulse control terminal (not shown) reset is asynchronous reset terminal, the reset state for the red traffic lights  output terminal r, g, y represent the three colors of traffic lights bright, the off state.)

本人用verilog编写的UDP协议，经测试可用。(I am prepared to use verilog UDP protocol, the test is available.)

说明：  Multiplexer 4 to 1 on Modelsim

SCAS `89 基准电路下载，包括Verilog和VHDL格式。verilog格式30个文件：包括S1238、S13207等;(SCAS `89 benchmark circuit downloads, including Verilog and VHDL formats. Verilog format 30 files: including S1238, S13207 and so on;)