RISC CPU IP CORE can be used to direct the development and application of the pr...

ASIC设计中常用的运算模块，如加减，常系数乘法，截断，饱和等。(some modules used in ASIC design.)

Verilog code for RS-(255,239) encoder.

基于VHDL语言的CORDIC算法实现，用于计算sin(x),cos(x)等，实测可用(Based on VHDL CORDIC algorithm, used to calculate sin (x), cos (x), etc., the measured available)

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现对一个十字路口的交通灯的控制，包括4个红绿灯和4个2位的数码倒计时器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board to realize a crossroads traffic lights control, including four traffic lights, and four 2-bit digital countdown device.

vhdl code for carry lookahead addder

Verilog-RISC CPU

Verilog 语言编写 PCI9054 控制器的接口电路，实现 PCI总线到本地 8 位总线的转接控制(The Verilog language writes the interface circuit of the PCI9054 controller to realize the transfer control of the PCI bus to the local 8 bit bus)

用verilog语言实现加密芯片DS28E01的调用操作命令。(Using Verilog language to achieve the encryption chip DS28E01 call operation commands.)

Package include hardware implementation of Lz77 algorithm

图像处理的中值滤波器，使用verilog开发环境编程实现。(Verilog development environment programming median filter)