RISC CPU IP CORE can be used to direct the development and application of the pr...

在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意-QuartusII warning solving

可在FPGA上运行的8051 IP core,是学习FPGA及SPOC的好资料。-FPGA can be run on 8051 IP core, is to learn from FPGA and SPOC good information.

verilog例子资源，对于初学者很有帮助。-verilog examples of resources are very useful for beginners.

SPI Verilog code with programmable clock

这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)

yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)

实现beep发出1234567的音乐声音-beep 123456

描述Bayer图像无损压缩的一种先进算法及其如何在FPGA上实现(Description Bayer Image is an advanced lossless compression algorithms in the FPGA to achieve and how)

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation