基于FPGA的vga显示

4位2选1多路选择器的设计与实现。nexy3开发板。本实验中用Verilog语句来描述。(Xilinx ISE 12.3.nexy3.)

实现beep发出1234567的音乐声音-beep 123456

印制线路板设计经验点滴-Printed Circuit Board Design Experience

RISC-DSP组合处理器设计优化[1].-RISC-DSP processor design portfolio optimization [1].

说明：  具有计时 设置时间 闹钟 秒表 功能的数字钟设计 外设矩阵键盘(Digital clock design peripheral matrix keyboard with the function of timing setting time alarm clock stopwatch)

基于NIOS II 的DE1开发板的VGA 控制器VGA控制模块主要控制VGA模块的开始和其运行的状态，需要写一个Avalon 从端口响应CPU的控制信号，继而控制整个模块的运行，-Based on the DE1 of the NIOS II development board VGA controller to control the VGA module VGA main control module and its operation began, and the need to write a response to Avalon from the CPU ports of the control signal, and then control the operation of the entire module,

verilog jtag源码及原理，还有debug模块。边界扫描等(verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.)

UART文件 包括发送器 接收器 fifo 测试文件(UART file includes a receiver transmitter fifo test files)

A program for a simple multiplexer using modelsimSE6.3

说明：  Verilog code for implementing simple ALU.