beep 123456

verilog编码器、计数器、加法器的程序(Verilog encoder, counter, adder procedures)

说明：  资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序，multifre1.vhd是倍频程序，multifre1.vwf是仿真波形文件，stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用，可以设置倍频数，修改实体参数N即可。(According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe that the procedure multiplier number, multifre1.vhd is the multiplier process, multifre1.vwf is the simulation waveform files, stp1.stp a virtual logic analyzer signaltap file. The multiplier process can be used directly, you can set the multiplier number, modify the parameter N can be solid.)

卷积码(2,1,7)编码器，一个输入，两个输出(Convolution code (2,1,7) encoder, an input and two outputs)

hbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu så s jekak o hfufuu ann anfuuan sjfk f4 77 57874 98 erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu så s jekak o hfufuu ann anfuuan sjfk f4 77 57874 98 erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu sås jekak o hfufuu ann anfuuan sjfk f4 77 57874 98 erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu så s jekak o hfufuu ann anfuuan sjfk f4 77 57874 98 erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu så s jekak o hfufuu ann anfuuan sjfk f4 77 57874 98erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje

基于FPGA的用verilog语言写的，改程序可产生不同调制系数和不同频率的AM波，长按按键切换调制度25 、50 、75 和短按按键切换调制信号频率1k、1.5k、2k、2.5k.(Based on the FPGA using verilog language, change the program can produce different coefficients and different frequency modulated AM wave, long press the button to switch the modulation of 25 , 50 , 75 and short press button to switch the modulation signal frequency 1k, 1.5k, 2k, 2.5k.)

两位独立数码管100进制计数器，每1秒计数一次。从0到99，到99后又回到0.-Two independent 100-band digital tube counters, every time 1 seconds count. From 0 to 99, to 99 and then back to 0.

对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)

VHDL黄金参考手册，能让你更好的学习了解VHDL语言(VHDL gold reference manual, can make you a better learn VHDL language)

三相电流滞环跟踪PWM逆变器。逆变电路负载电流与指令电流比较产生PWM波形。经验证可很好实现功能。(The three-phase hysteresis current tracking PWM inverter. Load current command current of the inverter circuit generating a PWM waveform. Proven functions well.)

第7章数字系统设计实例 7.1 半整数分频器的设计 7.2 音乐发生器 7.3 2FSK/2PSK信号产生器 7.4 实用多功能电子表 7.5 交通灯控制器 7.6 数字频率计-Chapter 7 Digital System Design Example 7.1-integer dividers designed Music Generator 7.2 7.3 2F SK/2PSK Signal Generator 7.4 Table practical multi-function electronic traffic signal controllers 7.5 7.6 Digital Cymometer