RISC

说明：  基于ofdm系统的各个模块的VHDL程序，软件是用的ISE仿真的。绝对有用。(Ofdm systems based on VHDL program of each module, the software is to use the ISE simulation. Absolutely useful.)

FPGA板上的锁存器PLL控制代码（verilog代码）(FPGA board latch the PLL control code (Verilog code))

上海大学 Verilog PPT 适合初学者看 推荐 -Shanghai University Verilog PPT look recommended for beginners

XVRWARE Library Xilinx Inc. The XVRWARE Synthesis library provides macros and synthesis examples for constructing TMR circuits in VHDL for the Virtex architecture

VIVADO SOC 使用文档 基于zynq 7020(vivado soc example text of zynq)

数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。(The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stopwatch count the seconds from the 00-00-00. Until you press stop key (key switch S2). Nixie tube stop count seconds. Press the start button (key switch S1), the digital control continue to count seconds. Press the reset button (core panel reset button) to restart the stopwatch count seconds from the 00-00-00.)

对MAX5250芯片进行控制，实现DA转换输出。(Controlling MAX5250 Chip)

VGA显示FPGA实现的VHDL语言的贪吃蛇游戏设计 本设计分为6个模块主要是扫描模块 VGA现实和控制模块 游戏设计的模块 电源模块等 用QUARTUS2仿真运行(VGA display FPGA VHDL language to realize the Snake game design The design is divided into six modules mainly scanning module VGA module power module and control module reality game design, etc. Simulation run with QUARTUS2)

频移键控FSK的Verilog实现，带测试文件，并在FPGA开发板上成功验证(Frequency Shift Keying FSK the Verilog implementation, with the test file, and successfully verified in FPGA development board)

ofdm的发射链路和接收链路的Verilog源代码，包括长短训练序列的生成，导频插入，加cp，ifft。(Source code of transmission link and reception link of OFDM)