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DE2_115_TV
这个代码主要实现了基于VHDL的关于TV方面的功能。(This code is the main achievement of the VHDL about aspects of the function based on TV.)
- 2013-03-06 21:49:22下载
- 积分:1
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Xilinx公司网站下的SDRAM Controller的参考设计,经过验证
Xilinx公司网站下的SDRAM Controller的参考设计,经过验证-Xilinx website of SDRAM Controller reference design, validated
- 2022-04-11 09:06:46下载
- 积分:1
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ytupn
Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.
- 2017-09-02 18:07:13下载
- 积分:1
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example
一个电子秒表,最大显示59.99,具有暂停和reset功能(An electronic stopwatch, the maximum display 59.99, with a pause and reset functions)
- 2013-12-17 12:28:14下载
- 积分:1
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VHDL 状态机的设计实例 ,不错的,对于搞清楚状态机是很有用的....
VHDL 状态机的设计实例 ,不错的,对于搞清楚状态机是很有用的.-VHDL state machine design examples, good for the state machine to figure out would be very useful.
- 2022-07-09 03:27:51下载
- 积分:1
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VHDL、Verilog HDL语言,是华为公司的技术指导书,希望对你有所帮助...
VHDL、Verilog HDL语言,是华为公司的技术指导书,希望对你有所帮助-VHDL、Verilog HDL
- 2022-01-28 23:23:37下载
- 积分:1
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基本逻辑门电路的设计方法,或门的VHDL的设计让你更容易步入VHDL的设计氛围中,简单的或门编制...
基本逻辑门电路的设计方法,或门的VHDL的设计让你更容易步入VHDL的设计氛围中,简单的或门编制-Basic logic gate circuit design methods, or the door of the VHDL design allows you to more easily into the VHDL design environment, the simple OR gate preparation
- 2022-01-30 19:12:35下载
- 积分:1
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LCD1602测试程序
实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)
- 2020-06-23 21:00:01下载
- 积分:1
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dds算法的fpga实现 altera
根据不同设置,输出不同频率的信号源...
dds算法的fpga实现 altera
根据不同设置,输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
- 2022-03-02 02:14:19下载
- 积分:1
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FIR_poroje
this project is about FIR FIlter By VHdl codes in the ISE.
- 2013-09-29 19:25:16下载
- 积分:1