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verilog8B10B
8b10b编码方式,verilog语言实现,有测试程序。能成功编码。没有环回验证,读者可自行编写环回验证测试程序。(8b10b encoding, verilog language, test procedures. Successful encoding. No loopback verification, readers can write your own loopback verification test procedures.)
- 2014-04-08 13:37:34下载
- 积分:1
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cppOrbitTools
tle转换为六根数的c++源代码,英文原版代码,测试可用(tle converted to six the number of c++ source code, the English original code, test available)
- 2021-03-16 10:49:21下载
- 积分:1
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Verilog-shift-mulfunction
FPGA verilog 实现任意位宽的移位相乘法,有符号小数或者有符号整数相乘。函数调用方式(FPGA verilog achieve any bit-wide shift multiplication , signed or signed decimal integer multiplication . Function call
)
- 2014-06-21 17:08:12下载
- 积分:1
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Dice_game
VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.
- 2011-02-22 22:07:59下载
- 积分:1
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encode_64_66
自编的64B/66B编码程序,下次上传解码程序。(the 64B/66B coding process is written by myself, i will upload the decoding process next time.)
- 2011-08-27 10:38:53下载
- 积分:1
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mvb_altera_may-02
altera mvb fpga sopc 设计参考文档,有一定价值(mvb fpga sopc Design scheme)
- 2015-01-15 17:15:33下载
- 积分:1
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15-04-0218-01-004a-ieee802-15-4-mac-overview
THE IMPLENTATION OF THE MAC PROTOCOL USING THE FPGA ALTERA 3
- 2013-04-18 20:04:49下载
- 积分:1
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arbiter_ip
Arbiter code for simulation purpose
- 2013-07-13 17:45:11下载
- 积分:1
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shumaguandongtai
VHDL的动态扫描显示六个数码管,包含分频代码产生25kHz的扫描信号作为时钟。(VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.)
- 2012-11-26 14:40:42下载
- 积分:1
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VHDL
用VHDL语言实现一Mealy型时序电路,并做时序仿真和功能仿真检验正确与否。(Implement a Mealy-type sequential circuits using VHDL language, and do functional simulation and timing simulation test correct.)
- 2014-03-20 14:44:28下载
- 积分:1