-
qam_64
64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核(64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS)
- 2021-03-02 23:29:33下载
- 积分:1
-
lisa-vhdl2va
通过modelsim仿真检测matlab生成滤波器效果。(Generate the filter through matlab and simulated by modelsim.)
- 2013-12-12 11:17:18下载
- 积分:1
-
GCD
Verilog 最大公约数设计RTL级代码和芯片设计图(Verilog GCD Design and synthesis layout )
- 2021-04-26 15:48:45下载
- 积分:1
-
tcpip_stack_v1_2
说明: 实现ARP、ICMP、UDP、TCP、IP和MAC全过程的传输,对TCP的连接、接收、发送、断开均经过测试,功能正常(Realize the transmission of ARP, ICMP, UDP, TCP, IP and MAC in the whole process, test the connection, reception, transmission and disconnection of TCP, and the function is normal)
- 2020-05-05 10:03:04下载
- 积分:1
-
开源软核处理器OpenRisc的SOPC设计
开源软核处理器OpenRisc的SOPC设计
- 2022-01-25 21:28:54下载
- 积分:1
-
Of PCM
对PCM编码的多路复用与解复用程序,VerilogHDL源程序-Of PCM-encoded multiplexing and demultiplexing process, VerilogHDL source
- 2022-02-05 07:01:51下载
- 积分:1
-
EC-67-XT_en
LED based video wall tech spec
- 2012-12-20 20:27:37下载
- 积分:1
-
uart_test
verilog实现UART收发功能,硬件平台为spartan 6,软件平台为ise14.7(verilog implement UART rx and tx function)
- 2017-10-07 16:34:13下载
- 积分:1
-
library
Library OLED SSD1305
- 2012-11-01 21:21:26下载
- 积分:1
-
serial_communication
说明: 串口操作源代码,本代码采用veilog hdl语言编写,并经过本人多次验证。(source code, the code used veilog HDL language, and after I repeatedly verified.)
- 2006-04-06 09:38:19下载
- 积分:1