Examples of VHDL language, including a variety of logic gate structure.

AD7991_7995_7999转换器说明(4-Channel, 12-/10-/8-Bit ADC with I2C-Compatible Interface in 8-Lead SOT-23)

16QAM,64QAM,256QAM调制下的球形译码(16QAM, 64QAM, 256QAM modulation sphere decoding)

xlinx fpga实现fft功能，利用ip核，包含源程序及完整工程文件，直接就能使用(The fft function xlinx fpga ip-core contains the source code and complete the project file, and can be used directly)

高速ADC及DAC接口的参考设计。在Xilinx FPGA上实现。(Reference design of xapp1071.)

用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)

spi-slave通信的vhdl实现及其仿真(VHDL implementation of spi-slave communication)

采用CORDIC算法的直接数字频率合成器的设计(CORDIC algorithm uses direct digital frequency synthesizer design)

代码文件夹： ARVI_FSM.v为顶层文件，用于模拟时用。 dataHex.dat 为模拟输入文件（只有10行，象征的意思。实际我们模拟时，dataHex.dat文件足有1个多GB） dataFormat.dat为输入文件对应的带格式的文件 使用modelsim模拟时，将dataHex.dat名字改为CPUContext.txt 结果: result.txt (Code folder: ARVI_FSM.v for top-level documents used for the simulation. dataHex.dat for analog input files (only 10 line, the meaning of the symbol. actual simulation we, dataHex.dat documents have more than one full GB) dataFormat.dat for the input file the corresponding file with modelsim simulation used to dataHex.dat name to CPUContext.txt results: result.txt)

ZardWars Files ------------------------------

AD采集模块,设计模块采集AD5270的输出数据(AD Collection module Design module to collect the output data of AD5270 )