用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS

用Verlog HDL编写的数字钟程序，包含时，分，秒，进位，解码，扫描显示等功能。-Written by Verlog HDL ，a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display.

说明：  使用Verilog HDL ，FM调制信号。(Using Verilog, HDL, and FM modulation signals.)

VHDL_COUNTING 0_9_LED 7 段 (ĐẾM 0 ĐẾN 9 HIỂN THỊ LED 7 ĐOẠN BẰNG NGÔN NGỮ VHDL)

使用ALTERA上DE2平台，使用Verilog描述，交通灯控制。-Using ALTERA on DE2 platform, use the Verilog description of the traffic light control.

等精度测试频率计，包括程序源代码以及相关注释-Precision test frequency meter, etc., including source code and related comments ......

VHDL cyclic redundancy check generator und receiver

在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.

vhdl program of matlab file converted to vhdl

说明：  在FPGA内利用verilog实现数字上变频(apply the verilog to implement the digital up frequency)

说明：  使用verilog实现ppm解码器，功能仿真通过，附设计说明，THU微纳电子系ic设计课大作业。(a ppm decoder written in VerilogHDL, a design document is available)