用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS

this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. -this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.

基于FPGA的JPEG图像压缩芯片设计 -FPGA-based JPEG image compression chip design

I2C的VHDL源码，从机模式，编译通过。-I2C the VHDL source code, from the mode, the compiler through.

parllel toserial out test bench

此文档包含 VHDL 的Vedic 乘数的详细内容。 它内容Vedic 乘数过程的详细的解释。

morris mano basic vhdl code in ise

VHDL实现交通灯-VHDL traffic lights

NIOS II IDE 编程， uart_txd测试程序，仅供参考。-NIOS II IDE programming, uart_txd testing procedures, for information purposes only.

TDM，就是时分复用。本程序完成4通道，没通道最多32路64K信号的交换，就是说可以完成32x4个电话信号交换(TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange)

说明：  配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)