这个程序执行的复用与解复用

二进制转十进制BCD码 Verilog语言 quartusII(Binary to decimal BCD code Verilog language quartusII)

I2C接口标准建模源码,I2C interface standard modeling source-I2C interface standard modeling source

This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

用Verilog描述了一款简单逻辑芯片74HC595的功能该芯片功能为：带输出锁存的8位移位寄存器(use the verilog to describe a simple chip 74HC595 with 8-Bit Serial-In, Parallel-Out Shift Reg and High-Current 3-State Outputs Reg)

说明：  FPGA串口实现。 发送和接受数据功能代码(FPGA serial interface. Send and receive data function code)

说明：  QSPI_FLASH_MODEL 可以设计时前端仿真使用(QSPI?_Flash_Model can be used in front-end simulation at design time)

Opencore的IP Core，有实际合成过，可以用，大家参考-Opencore of the IP Core, there is a practical synthesis that we could use, we refer to see

用VerilogHDL写的spi 核的例子(A simple example of SPI core using Verilog HDL)

基于FPGA的RS编码器设计，verilog hdl语言。(RS encoder FPGA-based design, verilog hdl language.)

使用VHDL汽车自动化技术VHDL代码1.镜旋转2.温度控制近期许多应用程序并通过VHDL它将会更容易