HDL的例子源代码3 / 5

这是用Verilog写的RS485通信程序，可以使用，希望大家能够互相交流，(This is a Verilog writing RS485 communication program, can be used, I hope we can communicate with each other,)

vs自定义插件开发,带卸载功能,经测试完全可用，分享给大家，可以学习！(vs custom plug-in development, with the uninstall feature, has been tested and is fully available for everyone to share, you can learn!)

用VHDL编写的计算器，能实现简单的加减乘除四则运算

基于VHDL实现加扰器解扰器的设计，与仿真。(VHDL-based scrambler descrambler design and simulation.)

该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐 (The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)

DAC VHDL code using SPI method

说明：  100个vhdl例子，对初学者很有用，可以用MAX+PLUS 2来编译仿真的(100 vhdl example, useful for beginners, you can use the MAX+ PLUS 2 to compile the simulation)

altera详细使用配置手册，有一定的参考价值，写的比较详细-altera in detail the use of manual configuration, has a certain reference value, a more detailed written

此为数学形态滤波器消燥的代码，用于一维信号，涉及一个具体的例子，需要的话可以自己修改，修改相应的结构元素。(This is a mathematical morphology filter away dry code, used to one dimensional signal, involving a concrete example, necessary can change ourselves, change the structure of the corresponding elements)

verilog延时电路的不同写法，和综合能否。可对比学习(Different wording verilog delay circuit, and comprehensive ability. Comparable learning)