HDL的例子源代码3 / 5

this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.

FPGA中FLASH配置控制源码,VHDL和Verilog(FPGA source code in the FLASH configuration control, VHDL and Verilog)

本人用verilog编写的UDP协议，经测试可用。(I am prepared to use verilog UDP protocol, the test is available.)

基于fpga的计数器模块 分频 可移植 完美实现(Perfect realization of frequency division and portability of counter module based on FPGA)

任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。-Arbitrary base frequency Verilog code, after compilation, the figures can be amended to change the frequency.

周立功sopc教程的视频资料，适合广大自学者学习-ZLG sopc video tutorial is suitable for the general self-learners to learn

用于串行到并行数据转换器的VHDL代码；当输入数据是串行的时，该代码是用于许多应用程序的位到字节转换的VHDL代码形成代码使用基于FPGA的LUT和D-RAM来存储数据，然后用时钟推送字节对齐的数据。

针对兆瓦级风电并网逆变器主电路研制中存在的并联扩容、开关频率较低和LCL滤波器难以优化设计等问题，提出了采用交流侧串接电感再进行并联的均流方案，采用载波移相技术提高变流器的等效开关频率，提出了LCL滤波器的设计原则，并给出了上述设计的理论依据和实现方法。通过对2兆瓦风电变流器主电路的仿真验证了上述技术方案。(MW-class wind power for grid-inverter main circuit of the parallel development of existing capacity, a lower switching frequency and LCL filter design difficult to optimize the problem, a series inductor AC side in parallel are further flow program, the use of carrier phase-shifting technology to enhance the equivalent converter switching frequency, a LCL filter design principles, and gives the above-mentioned theoretical basis for the design and implementation. 2 MW of wind power converter main circuit simulation program to verify the above-mentioned technology.)

altera嵌入式设计大赛文章，车载cots设计实现-Embedded Design Contest altera article, cots Car Design

对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)