常用小程序一应俱全

UART串口的verilog源代码，完全正确...........(UART serial Verilog source code, completely correct ...........)

能实现输入0.5 1 5块钱的累加，然后对应购买的商品价格进行比较，显示找的钱数或错误灯(MY English is very good)

实现PWM波型....使用VHDL语言-Realization of PWM waveform using the VHDL language ....

ask调制，基于VHDL仿真平台，解调同样给出，此程序经过验证-ask modulation, based on VHDL simulation platform, demodulator is the same, this procedure proven

自编的64B/66B编码程序，下次上传解码程序。(the 64B/66B coding process is written by myself, i will upload the decoding process next time.)

实现自然对数运算的cordic算法的matlab浮点仿真，以及针对FPGA硬件平台的定点仿真测试(Achieve natural logarithm of cordic algorithm matlab floating point emulation, and FPGA hardware platform for fixed-point simulation testing)

在quaters下写的比较数的大小输出，verilog语言写的，具有状态机和存储器-Written in the quaters of the size of the comparator output, verilog language written with the state machine and memory

quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE

设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter

单口RAM带CLR信号的verilog程序。很详细的.(Single-port RAM with a CLR signal)